AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 47

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and
REJ60 set to 1, the filter response shown in Figure 53 is achieved.
The output data rate is unchanged but the 50 Hz/60 Hz ± 1 Hz
rejection improves to 73 dB typically.
FAST SETTLING MODE (SINC
In fast settling mode, the settling time is close to the inverse of
the first filter notch; therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is equal to 1/output data rate. Therefore, the
conversion time is constant when converting on a single channel
or when converting on several channels. There is no added
latency when switching channels.
Enable the fast settling mode using Bit AVG1 and Bit AVG0 in
the mode register. In fast settling mode, a postfilter is included
after the sinc
depending on the settings of the AVG1 and AVG0 bits.
Output Data Rate and Settling Time, Sinc
With chop disabled, the output data rate is
f
f
Avg is the average.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
If AVG1 = AVG0 = 0, the fast settling mode is not enabled.
In this case, Equation 1 is not relevant.
ADC
CLK
is the master clock (4.92 MHz nominal).
is the output data rate.
f
–100
–110
–120
ADC
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
= f
0
CHOP
CLK
4
filter. The postfilter averages by 2, 8, or 16,
/((4 + Avg − 1) × 1024 × FS[9:0])
Figure 54. Fast Settling Mode, Sinc
(FS[9:0] = 96, Chop Enabled, REJ60 = 1)
25
MODULATOR
Figure 53. Sinc
50
FREQUENCY (Hz)
ADC
SINC
3
Filter Response
75
3
/SINC
4
FILTER)
4
100
POST FILTER
4
Filter
4
Filter
125
150
Rev. B | Page 47 of 56
(1)
The settling time is equal to
Table 34 lists sample FS words and the corresponding output
data rates and settling times.
Table 34. Examples of Output Data Rates and the
Corresponding Settling Time (Fast Settling Mode, Sinc
FS[9:0]
96
30
6
5
When the analog input channel is changed, there is no additional
delay in generating valid conversions—the device functions as a
zero latency ADC.
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect the
change and continues to output conversions. If the step change
is synchronized with the conversion, only fully settled results
are output from the ADC. However, if the step change is asyn-
chronous to the conversion process, there is one intermediate
result, which is not completely settled (see Figure 56).
The output data rate is the same for chop enabled and chop
disabled in fast settling mode. However, when chop is enabled,
the settling time equals
Therefore, if chop is enabled, the sinc
is set to 6, and averaging by 16 is enabled. The output data rate
is equal to 42.1 Hz when the master clock equals 4.92 MHz.
Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms and
the settling time is equal to 47.5 ms.
CONVERSIONS
ANALOG
OUTPUT
INPUT
t
t
ADC
SETTLE
SETTLE
CHANNEL
Average
16
16
16
16
Figure 56. Step Change on Analog Input, Sinc
= 1/f
= 2/f
CH A CH A CH A
ADC
ADC
CHANNEL A
Figure 55. Fast Settling, Sinc
Output Data Rate (Hz)
2.63
8.4
42.1
50.53
CH B
4
1/
CH B
filter is selected, FS[9:0]
f
ADC
CHANNEL B
4
Filter
CH B
Settling Time (ms)
380
118.75
23.75
19.79
CH B
4
Filter
CH B CH B
AD7193
VALID
1/
f
ADC
4
)