AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 24

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
Bit Location
MR12
MR11
MR10
MR9 to MR0
Table 21. Operating Modes (MD)
MD2
0
0
0
0
MD1
0
0
1
1
MD0
0
1
0
1
Bit Name
CLK_DIV
Single
REJ60
FS9 to FS0
Mode
Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs
conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go
low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the commun-
ications register to 1, which enables continuous read. When continuous read is enabled, the conversions are
automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to
output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of
the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent
conversions are available at the selected output data rate, which is dependent on filter choice.
Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single
conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then
performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in
the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data
register until another conversion is performed. RDY remains active (low) until the data is read or another conversion
is performed.
Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks
continue to be provided.
Power-down mode. In power-down mode, all AD7193 circuitry, except the bridge power-down switch, is powered
down. The bridge power-down switch remains active because the user may need to power up the sensor prior to
powering up the AD7193 for settling reasons. The external crystal, if selected, remains active.
Description
Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this
bit to 0. When performing internal full-scale calibrations, this bit must be set when AV
4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used
while performing the calibration. When AV
the CLK_DIV bit when performing internal full-scale calibrations.
Single cycle conversion enable bit. When this bit is set, the AD7193 settles in one conversion cycle so
that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are
enabled or when the single conversion mode is selected. If the average + decimate filter is enabled, this
bit (single) does not have an effect on the conversions unless chopping is also enabled.
This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a
filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/
60 Hz rejection.
Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter
cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In
association with the gain selection, they also determine the output noise and, therefore, the effective
resolution of the device (see Table 7 through Table 15).
When chop is disabled, fast settling mode is disabled and continuous conversion mode is selected.
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and
MCLK is the master clock frequency.
With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop
disabled and fast settling mode disabled, the first notch frequency is equal to the output data rate when
converting on a single channel.
When chop is enabled (fast settling mode disabled)
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and
MCLK is the master clock frequency.
With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N
is the order of the sinc filter. The first notch frequency of the sinc filter is equal to
The chopping introduces notches at odd integer multiples of
Output Data Rate = (MCLK/1024)/FS
Output Data Rate = (MCLK/1024)/(N × FS)
N × Output Data Rate
Output Data Rate/2
Rev. B | Page 24 of 56
DD
is greater than or equal to 4.75 V, it is not compulsory to set
DD
is less than