AD7631BCPZ Analog Devices Inc, AD7631BCPZ Datasheet - Page 30

IC,A/D CONVERTER,SINGLE,18-BIT,CMOS,LLCC,48PIN

AD7631BCPZ

Manufacturer Part Number
AD7631BCPZ
Description
IC,A/D CONVERTER,SINGLE,18-BIT,CMOS,LLCC,48PIN
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet

Specifications of AD7631BCPZ

Number Of Bits
18
Sampling Rate (per Second)
250k
Data Interface
Serial, Parallel
Number Of Converters
1
Power Dissipation (max)
120mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD7631
MICROPROCESSOR INTERFACING
The AD7631 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing
applications interfacing to a digital signal processor. The
AD7631 is designed to interface with a parallel 8-bit or 18-bit wide
interface, or with a general-purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used with
the AD7631 to prevent digital noise from coupling into the ADC.
SPI Interface
The AD7631 is compatible with SPI and QSPI digital hosts and
DSPs, such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x.
Figure 48 shows an interface diagram between the AD7631 and
the SPI-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7631 acts as a slave device, and data must
be read after conversion. This mode also allows the daisy-chain
feature. The convert command could be initiated in response to
an internal timer interrupt.
SCCLK
CNVST
SCCS
BUSY
SCIN
BIPOLAR = 0 OR 1
TEN = 0 OR 1
X
t
t
33
31
t
31
START
1
HW/SW = 0
MODE[1:0] = 3
t
34
BIPOLAR
2
INVSCLK = 0
PD = 0
3
TEN
Figure 47. Serial Configuration Port Timing
4
t
PD
35
t
37
t
5
36
Rev. A | Page 30 of 32
X
6
X
The reading process can be initiated in response to the end-of-
conversion signal (BUSY going low) using an interrupt line of
the DSP. The serial peripheral interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable
(TIMOD) = 0 by writing to the SPI control register (SPICLTx).
It should be noted that to meet all timing requirements, the SPI
clock should be limited to 17 Mbps allowing it to read an ADC
result in less than 1 μs. When a higher sampling rate is desired,
use one of the parallel interface modes.
OB/2C
7
8
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 48. Interfacing the AD7631 to SPI Interface
9
MODE[1:0]
EXT/INT
RD
INVSCLK
AD7631*
SDOUT
SDCLK
CNVST
BUSY
t
8
CS
X
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
ADSP-219x*

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