AD7631BCPZ Analog Devices Inc, AD7631BCPZ Datasheet - Page 5

• Manufacturer Part Number: AD7631BCPZ
• Description: IC,A/D CONVERTER,SINGLE,18-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7631BCPZ

• Number Of Bits: 18
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 120mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V
Table 3.
Parameter
CONVERSION AND RESET (See Figure 35 and Figure 36)
PARALLEL INTERFACE MODES (See Figure 37 and Figure 39)
MASTER SERIAL INTERFACE MODES
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES
1
2
In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay
CS Low to SDOUT Delay
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SDCLK Last Edge to SYNC Delay
CS High to SYNC HIGH-Z
CS High to Internal SDCLK HIGH-Z
CS High to SDOUT HIGH-Z
BUSY High in Master Serial Read After Convert
CNVST Low to SYNC Delay, Read After Convert
SYNC Deasserted to BUSY Low Delay
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
CNVST Low to SYNC Delay, Read During Convert
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period
Internal SDCLK High
Internal SDCLK Low
(See Figure 44, Figure 45, and Figure 47)
2
2
2
2
2
2
1
(See Figure 41 and Figure 42)
1
2
1
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Symbol
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t
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1
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REF
= 5 V; all specifications T
Min
10
4.0
10
2.32
10
20
2
3
30
15
10
4
5
5
5
2
5
5
25
10
10
L
of 10 pF; otherwise, the load is 60 pF maximum.
Typ
2
530
See Table 4
1.5
25
MIN
to T
MAX
, unless otherwise noted.
Max
35
1.68
1.68
1.65
40
15
10
10
10
45
10
10
10
18
AD7631
Unit
ns
μs
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