AD7983BCPZ-RL Analog Devices Inc, AD7983BCPZ-RL Datasheet - Page 19

• Manufacturer Part Number: AD7983BCPZ-RL
• Description: IC,A/D CONVERTER,SINGLE,16-BIT,LLCC,10PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7983BCPZ-RL

• Number Of Bits: 16
• Sampling Rate (per Second): 1.33M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 12mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-WFDFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7983s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7983s is shown in
Figure 30, and the corresponding timing is given in Figure 31.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion
time to avoid the generation of the busy signal indicator.
SCK
SDO
ACQUISITION
CNV
SDI(CS1)
t
SSDICNV
SDI(CS2)
t
HSDICNV
CONVERSION
t
CONV
t
EN
SDI
AD7983
Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
CNV
SCK
D15
1
t
HSDO
SDO
D14
2
D13
3
t
DSDO
t
SCKL
t
Rev. A | Page 19 of 24
14
SCKH
SDI
t
SCK
15
D1
AD7983
CNV
SCK
t
CYC
When the conversion is complete, the AD7983 enters the
acquisition phase and goes into standby mode. Each ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7983
can be read.
ACQUISITION
16
D0
t
SDO
ACQ
D15
17
CS2
CS1
CONVERT
DATA IN
CLK
DIGITAL HOST
D14
18
30
31
D1
32
D0
t
DIS
AD7983