AD9254BCPZRL7-150 Analog Devices Inc, AD9254BCPZRL7-150 Datasheet
AD9254BCPZRL7-150
Specifications of AD9254BCPZRL7-150
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AD9254BCPZRL7-150 Summary of contents
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FEATURES 1.8 V analog supply operation 1 3.3 V output supply SNR = 71.8 dBc (72.8 dBFS MHz input SFDR = 84 dBc to 70 MHz input Low power: 430 mW @ 150 MSPS Differential input ...
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AD9254 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes ...
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AD9254 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE-RATIO (SNR ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic ...
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AD9254 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted. Table 4. Parameter 1 CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Conversion Rate, DCS Disabled CLK Period CLK Pulse Width High, DCS Enabled CLK Pulse Width ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0 +2.0 V DRVDD to DGND −0 +3.9 V AGND to DGND −0 +0.3 V AVDD to DRVDD −3 +2.0 V ...
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AD9254 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Description Pin No. Mnemonic 0, 21, 23, 29, 32, AGND 37, 41 45, 46 (LSB) to D13 (MSB 16, 47 DRGND 8, ...
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EQUIVALENT CIRCUITS VIN Figure 4. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 5. Equivalent Clock Input Circuit DRVDD 1kΩ SDIO/DCS Figure 6. Equivalent SDIO/DCS Input Circuit DRVDD DRGND Figure 7. Equivalent Digital Output Circuit SCLK/DFS OEB PDWN ...
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AD9254 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled internal reference p-p differential input; AIN = −1.0 dBFS; 64k sample 25°C, unless otherwise noted ...
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SNR = 69.3dBc (70.3dBFS) –20 ENOB = 11.3 BITS SFDR = 79dBc –40 –60 –80 –100 –120 0 18.75 37.50 FREQUENCY (MHz) Figure 18. AD9254 Single-Tone FFT with f 0 150MSPS f = 29.1MHz @ ...
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AD9254 0 150MSPS f = 169.1MHz @ –7dBFS IN1 f = 172.1MHz @ –7dBFS IN2 –20 SFDR = 83dBc (90dBFS) WoIMD3 = –83dBc (90dBFS) –40 –60 –80 –100 –120 0 18.75 37.50 FREQUENCY (MHz) Figure 24. AD9254 Two-Tone FFT with ...
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OTUPUT CODE Figure 30. AD9254 DNL with f = 10.3 MHz IN 14336 16384 Rev Page AD9254 ...
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AD9254 THEORY OF OPERATION The AD9254 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. ...
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DIFFERENTIAL INPUT CONFIGURATIONS Optimum performance is achieved by driving the AD9254 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 ...
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AD9254 0.1µF 2V p-p P 0.1µ 0.1µF Table 9. Reference Configuration Summary Selected Mode SENSE Voltage External Reference AVDD Internal Fixed Reference VREF Programmable Reference 0 VREF Internal Fixed Reference AGND to 0.2 V ...
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VIN+ ADC CORE VIN– VREF 0.1µF 0.1µF SELECT LOGIC SENSE 0.5V AD9254 Figure 37. Internal Reference Configuration VIN+ ADC CORE VIN– VREF 0.1µF 0.1µF R2 SELECT LOGIC SENSE R1 Figure 38. Programmable Reference Configuration If the internal reference of the ...
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AD9254 MINI-CIRCUITS ADT1–1WT, 1:1Z 0.1µF 0.1µF XFMR CLOCK INPUT 100Ω 50Ω 0.1µF SCHOTTKY 0.1µF DIODES: HMS2812 Figure 41. Transformer Coupled Differential Clock If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal ...
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The DCS can be enabled or disabled by setting the SDIO/DCS pin when operating in the external pin mode (see Table 10), or via the SPI, as described in Table 13. Table 10. Mode Selection (External Pin Mode) Voltage at ...
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AD9254 Standby Mode When using the SPI port interface, the user can place the ADC in power-down or standby modes. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required (see the ...
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SERIAL PORT INTERFACE (SPI) The AD9254 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending ...
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AD9254 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 to Address 0x02), ...
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MEMORY MAP REGISTER TABLE Table 15. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first 0 = Off (Default chip_id 02 chip_grade Open Open Device ...
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AD9254 Addr. Bit 7 (Hex) Parameter Name (MSB) Flexible ADC Functions 10 offset 0D test_io 14 output_mode Output Driver Configuration 00 for DRVDD = 2 3 for DRVDD = 1 output_phase Output Clock Polarity ...
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LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9254 recommended that two separate supplies be used: one for analog (AVDD, 1.8 V nominal) and one for digital (DRVDD, 1 3.3 V nominal). If ...
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AD9254 EVALUATION BOARD The AD9254 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configu- rations. The converter can be driven differentially through a double balun configuration (default) or through the ...
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DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9254 Rev. A evaluation board. POWER Connect the switching power supply that is supplied in the evaluation kit ...
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AD9254 To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed, and/or changed: 1. Remove C1 and C2 in the default analog input path. 2. Populate R3 ...
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SCHEMATICS RC0402 RC0402 RC040 2 RC040 2 RC0402 CC0402 2 HSMS281 2 HSMS281 RC0402 CC0402 CC0402 RC060 3 RC060 3 Figure 53. Evaluation Board Schematic, DUT Analog Inputs Rev Page AD9254 CC0402 RC060 3 RC060 ...
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AD9254 Figure 54. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface RC060 3 Rev Page ...
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CC0402 CC0402 RC0402 RC060 3 CC0402 CC0402 RC060 3 RC060 3 Figure 55. Evaluation Board Schematic, DUT Clock Input CC0402 CC0402 CC0402 RC0402 RC0402 RC0402 RC0402 S0 S10 GND_PAD ...
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AD9254 RC0603 SDO_CHA RC0603 CSB1_CHA RC0603 SDI_CH A RC0603 SCLK_CHA RC0603 RC0603 RC0603 RC0603 RC0603 1 2 PICVCC PICVCC 3 4 GP1 GP1 5 6 GP0 GP0 7 8 MCLR-GP3 MCLR-GP3 RC060 Figure 56. Evaluation Board Schematic, ...
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GND GND 1 1 GND GND GND CR500 1 2 Figure 57. Evaluation Board Schematic, Power Supply Inputs Rev Page AD9254 TP509 TP512 TP511 TP510 ...
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AD9254 EVALUATION BOARD LAYOUT Figure 58. Evaluation Board Layout, Primary Side Figure 59. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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Figure 60. Evaluation Board Layout, Ground Plane Figure 61. Evaluation Board Layout, Power Plane Rev Page AD9254 ...
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AD9254 Figure 63. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image) Figure 62. Evaluation Board Layout, Silkscreen Primary Side Rev Page ...
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BILL OF MATERIALS Table 16. Evaluation Board Bill of Materials (BOM) Omit Item Qty. (DNP) Reference Designator 1 1 AD9246CE_REVA 2 24 C1, C2, C509, C510, C511, C512, C514, C515, C516, C517, C528, C530, C532, C533, C538, C539, C540, C542, ...
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AD9254 Omit Item Qty. (DNP) Reference Designator 28 1 P501 29 6 R1, R6, R563, R565, R574, R577 30 5 R2, R5, R561, R562, R571 6 R10, R11, R12, R535, R536, R575 R7, R8, ...
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Omit Item Qty. (DNP) Reference Designator 60 1 U502 61 1 U503 62 2 U504, U505 63 1 U506 64 1 U507 65 1 U508 66 1 U509 67 1 U510 68 1 U511 (or Z500) Total 128 107 Device ...
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... PLANE ORDERING GUIDE Model Temperature Range 1, 2 AD9254BCPZ-150 –40°C to +85° AD9254BCPZRL7–150 –40°C to +85°C AD9254-150EBZ Pb-free part required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...