AD9254BCPZRL7-150 Analog Devices Inc, AD9254BCPZRL7-150 Datasheet - Page 19

• Manufacturer Part Number: AD9254BCPZRL7-150
• Description: IC,A/D CONVERTER,SINGLE,14-BIT,LLCC,48PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9254BCPZRL7-150

• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 3
• Power Dissipation (max): 470mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9254-150EBZ - BOARD EVALUATION FOR AD9254
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DCS can be enabled or disabled by setting the SDIO/DCS
pin when operating in the external pin mode (see Table 10), or
via the SPI, as described in Table 13.
Table 10. Mode Selection (External Pin Mode)
Voltage at Pin
AGND
AVDD
JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (f
In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF under-
sampling applications are particularly sensitive to jitter, as
shown in Figure 46.
Treat the clock input as an analog signal in cases where aperture
jitter can affect the dynamic range of the AD9254. Power supplies
for clock drivers should be separated from the ADC output
driver supplies to avoid modulating the clock signal with digital
noise. The power supplies should also not be shared with analog
input circuits, such as buffers, to avoid the clock modulating onto
the input signal or vice versa. Low jitter, crystal-controlled oscil-
lators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.
Refer to Application Notes AN-501, Aperture Uncertainty and
ADC System Performance; and
the Effects of Clock Phase Noise and Jitter, for more in-depth
information about jitter performance as it relates to ADCs.
SNR = −20 log (2π × f
75
70
65
60
55
50
45
40
1
IN
PERFORMANCE
Figure 46. SNR vs. Input Frequency and Jitter
) due to jitter (t
MEASURED
Binary (default)
Twos complement
SCLK/DFS
INPUT FREQUENCY (MHz)
10
IN
× t
J
) is calculated as follows:
AN-756,
J
)
Sampled Systems and
100
SDIO/DCS
DCS disabled
DCS enabled
(default)
0.05ps
0.20ps
0.5ps
1.0ps
1.50ps
2.00ps
2.50ps
3.00ps
1000
Rev. 0 | Page 19 of 40
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9254 is proportional to its sample
rate (see Figure 47). The digital power dissipation is determined
primarily by the strength of the digital drivers and the load on each
output bit. Maximum DRVDD current (I
where N is the number of output bits, 14 in the AD9254.
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption. The data in Figure 47 was taken under the same
operating conditions as the data for the Typical Performance
Characteristics section, with a 5 pF load on each output driver.
Power-Down Mode
By asserting the PDWN pin high, the AD9254 is placed in power-
down mode. In this state, the ADC typically dissipates 1.8 mW.
During power-down, the output drivers are placed in a high
impedance state. Reasserting the PDWN pin low returns the
AD9254 to its normal operational mode. This pin is both 1.8 V
and 3.3 V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling capaci-
tors on REFT and REFB, it takes approximately 0.25 ms to fully
discharge the reference buffer decoupling capacitors and 0.35 ms to
restore full operation.
Figure 47. AD9254 Power and Current vs. Clock Frequency f
I
500
480
460
440
420
400
380
360
340
320
300
DRVDD
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
=
V
DRVDD
CLK
×
CLOCK FREQUENCY (MHz)
/2. In practice, the DRVDD current is
C
LOAD
I (DRVDD)
I (AVDD)
POWER
×
f
CLK
2
×
N
DRVDD
) can be calculated as
AD9254
IN
= 30 MHz
300
250
200
150
100
50
0