AD9254BCPZRL7-150 Analog Devices Inc, AD9254BCPZRL7-150 Datasheet - Page 27

• Manufacturer Part Number: AD9254BCPZRL7-150
• Description: IC,A/D CONVERTER,SINGLE,14-BIT,LLCC,48PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9254BCPZRL7-150

• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 3
• Power Dissipation (max): 470mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9254-150EBZ - BOARD EVALUATION FOR AD9254
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9254 Rev. A evaluation board.
POWER
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching out to
70 MHz. For more bandwidth response, the differential capacitor
across the analog inputs can be changed or removed (see Table 8).
The common mode of the analog inputs is developed from the
center tap of the transformer via the CML pin of the ADC (see
the Analog Input Considerations section).
VREF
VREF is set to 1.0 V by tying the SENSE pin to ground via
JP507 (Pin 1 and Pin 2). This causes the ADC to operate in
2.0 V p-p full-scale range. A separate external reference option
is also included on the evaluation board. Connect JP507
between Pin 2 and Pin 3, connect JP501, and provide an external
reference at E500. Proper use of the VREF options is detailed
in the Voltage Reference section.
RBIAS
RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.
CLOCK
The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1
impedance ratio transformer (T503) that adds a very low amount
of jitter to the clock path. The clock input is 50 Ω terminated
and ac-coupled to handle single-ended sine wave inputs. The
transformer converts the single-ended input to a differential
signal that is clipped before entering the ADC clock inputs.
PDWN
To enable the power-down feature, connect JP506, shorting the
PDWN pin to AVDD.
CSB
The CSB pin is internally pulled-up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip
into serial pin mode, and enable the SPI information on the
SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in
the always enabled mode.
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SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets the
data format of the outputs. If the pin is left floating, the pin is
internally pulled down, setting the default condition to binary.
Connecting JP2 Pin 2 and Pin 3 sets the format to twos comple-
ment. If the SPI port is in serial pin mode, connecting JP2 Pin 1
and Pin 2 connects the SCLK pin to the on-board SPI circuitry
(see the Serial Port Interface (SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port
is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the
SDIO pin to the on-board SPI circuitry (see the Serial Port
Interface (SPI) section).
ALTERNATIVE CLOCK CONFIGURATIONS
A differential LVPECL clock can also be used to clock the ADC
input using the
the components listed in Table 16 need to be populated. Consult
the
To configure the analog input to drive the AD9515 instead of
the default transformer option, the following components need
to be added, removed, and/or changed.
1.
2.
3.
If using an oscillator, two oscillator footprint options are also
available (OSC500) to check the performance of the ADC.
JP508 provides the user flexibility in using the enable pin, which
is common on most oscillators. Populate OSC500, R575, R587,
and R588 to use this option.
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
This section provides a brief description of the alternative
analog input drive configuration using the AD8352. When
using this particular drive option, some components need to be
populated, as listed in Table 16. For more details on the
differential driver, including how it works and its optional pin
settings, consult the
AD9515
Remove R507, R508, C532, and C533 in the default clock
path.
Populate R505 with a 0 Ω resistor and C531 in the default
clock path.
Populate R511, R512, R513, R515 to R524, U500, R580,
R582, R583, R584, C536, C537, and R586.
data sheet for further information.
AD9515
AD8352
(U500). When using this drive option,
data sheet.
AD9254
AD8352