AD9272BSVZ-40 Analog Devices Inc, AD9272BSVZ-40 Datasheet - Page 31

• Manufacturer Part Number: AD9272BSVZ-40
• Description: 12Bit 40 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZ-40

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 40M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ADC
The AD9272 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and output clocks.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9272 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 54 shows the preferred method for clocking the AD9272.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50 MHz, is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9272 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9272, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 55. The AD951x family of clock drivers offers excellent
jitter performance.
50Ω RESISTOR IS OPTIONAL.
VFAC3
3.3V
VFAC3
OUT
3.3V
OUT
50Ω
Figure 54. Transformer-Coupled Differential Clock
50Ω 100Ω
0.1µF
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Figure 55. Differential PECL Sample Clock
0.1µF
0.1µF
ADT1-1WT, 1:1Z
MINI-CIRCUITS
CLK
CLK
PECL DRIVER
XFMR
0.1µF
AD951x FAMILY
240Ω
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
240Ω
100Ω
0.1µF
0.1µF
CLK+
CLK–
AD9272
CLK+
CLK–
ADC
AD9272
ADC
Rev. C | Page 31 of 44
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In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 57). Although the
CLK+ input circuit supply is AVDDx (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9272 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9272. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See Table 17 for more details on
using this feature.
50Ω RESISTOR IS OPTIONAL.
*
*
50Ω RESISTOR IS OPTIONAL.
50Ω RESISTOR IS OPTIONAL.
VFAC3
VFAC3
3.3V
3.3V
OUT
OUT
VFAC3
3.3V
OUT
50Ω
Figure 57. Single-Ended 1.8 V CMOS Sample Clock
Figure 58. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
0.1µF
*
50Ω
50Ω
Figure 56. Differential LVDS Sample Clock
0.1µF
0.1µF
0.1µF
0.1µF
*
*
CLK
CLK
CLK
CLK
CLK
CLK
LVDS DRIVER
CMOS DRIVER
CMOS DRIVER
AD951x FAMILY
AD951x FAMILY
AD951x FAMILY
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9272
CLK+
CLK–
AD9272
AD9272
AD9272
ADC
ADC
ADC