AD9380KSTZ-150 Analog Devices Inc, AD9380KSTZ-150 Datasheet - Page 13

• Manufacturer Part Number: AD9380KSTZ-150
• Description: IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the ADCs producing a
black output (Code 0x00) when the known black input is
present. The offset then remains in place when other signal
levels are processed, and the entire signal is shifted to eliminate
offset errors.
In most pc graphics systems, black is transmitted between active
video lines. With CRT displays, when the electron beam has
completed writing a horizontal line on the screen (at the right
side), the beam is deflected quickly to the left side of the screen
(called horizontal retrace) and a black signal is provided to
prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of HSYNC. Fortunately, there is virtually
always a period following HSYNC, called the back porch, where
a good black reference is provided. This is the time when
clamping should be done.
Clamp timing employs the AD9380 internal clamp timing
generator. The clamp placement register is programmed with
the number of pixel periods that should pass after the trailing
edge of HSYNC before clamping starts. A second register
(clamp duration) sets the duration of the clamp. These are both
8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of HSYNC because, though HSYNC duration can vary widely,
the back porch (black reference) always follows HSYNC. A
good starting point for establishing clamping is to set the clamp
placement to 0x08 (providing 8 pixel periods for the graphics
signal to stabilize after sync) and to set the clamp duration to
0x14 (giving the clamp 20 pixel periods to re-establish the black
reference). For three-level syncs embedded on the green
channel, it is necessary to increase the clamp placement to
beyond the positive portion of the sync. For example, a good
clamp placement (Register 0x19) for a 720p input is 0x26. This
delays the start of clamp by 38 pixel clock cycles after the rising
edge of the three-level sync, allowing plenty of time for the
signal to return to a black reference.
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capa-
citor affects the performance of the clamp. If it is too small,
there is a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
then it takes excessively long for the clamp to recover from a
large change in the incoming signal offset. The recommended
value (47 nF) results in recovering from a step error of 100 mV
to within ½ LSB in 10 lines with a clamp duration of 20 pixel
periods on a 75 Hz SXGA signal.
Rev. 0 | Page 13 of 60
YUV Clamping
YUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be
at the midpoint of the graphics signal rather than at the bottom.
For these signals, it can be necessary to clamp to the midscale
range of the ADC range (128) rather than thebottom of the
ADC range (0).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0x1B [7:5]. The midscale reference
voltage is internally generated for each converter.
Auto-Offset
The auto-offset circuit works by calculating the required offset
setting to yield a given output code during clamp. When this
block is enabled, the offset setting in the I
clamp code rather than an actual offset. The circuit compares
the output code during clamp to the desired code and adjusts
the offset up or down to compensate.
The offset on the AD9380 can be adjusted automatically to a
specified target code. Using this option allows the user to set the
offset to any value and be assured that all channels with the
same value programmed into the target code match. This
eliminates any need to adjust the offset at the factory. This
function is capable of running continuously any time the clamp
is asserted.
There is an offset adjust register for each channel, namely the
offset registers at the 0x08, 0x0A, and 0x0C addresses. The
offset adjustment is a signed (twos complement) number with a
±64 LSB range. The offset adjustment is added to whatever
offset the auto-offset comes up with. For example, using a
ground clamp, the target code is set to 4. To get this code, the
auto-offset generates an offset of 68. If the offset adjustment is
set to +10, the offset sent to the converter is 78. Likewise, if the
offset adjust is set to −10, the offset sent to the converter is +58.
Refer to Application Note
Offset Function of the AD9880,
to use this function.
Sync-on-Green (SOG)
The SOG input operates in two steps. First, it sets a baseline
clamp level from the incoming video signal with a negative
peak detector. Second, it sets the sync trigger level to a
programmable level (typically 150 mV) above the negative
peak. The SOG input must be ac-coupled to the green analog
input through its own capacitor. The value of the capacitor must
be 1 nF ± 20%. If SOG is not used, this connection is not
required. Note that the SOG signal is always negative polarity.
AN-775, Implementing the Auto-
for a detailed description of how
2
C is seen as a desired
AD9380