AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 38

• Manufacturer Part Number: AD9516-5/PCBZ
• Description: Clock IC With 2.5GHz On-chip VCO EB
• Manufacturer: Analog Devices Inc

Specifications of AD9516-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-5
• Primary Attributes: 2 Inputs, 14 Outputs
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
Let
Δ
Δ
T
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15:
Δ
Δ
Case 2
For Φ ≥ 16:
Δ
Δ
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 42 shows the results of setting such a coarse
offset between outputs.
DIVIDER 0
DIVIDER 1
DIVIDER 2
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 3 and Channel Divider 4 each drive a pair of
LVDS outputs, giving four LVDS outputs (OUT6 to OUT9).
Alternatively, each of these LVDS differential outputs can be
configured individually as a pair (A and B) of CMOS single-
ended outputs, providing for up to eight CMOS outputs. By default,
the B output of each pair is off but can be turned on as desired.
Channel Divider 3 and Channel Divider 4 each consist of two
cascaded, 1 to 32, frequency dividers. The channel frequency
division is D
have DCC enabled by default, but this function can be disabled,
if desired, by setting the DCCOFF bit of the channel. A coarse
phase offset or delay is also programmable (see the Phase Offset
or Coarse Time Delay (Divider 3 and Divider 4) section). The
channel dividers operate up to 1600 MHz. The features and
settings of the dividers are selected by programming the
appropriate setup and control registers (see Table 47 and Table 48
through Table 57).
DIVIDER INPUT
t
c
X
t
c
t
c
= delay (in seconds).
= Φ × T
= (Φ − 16 + M + 1) × T
= delay (in cycles of clock signal at input to D
= Δ
= Δ
= period of the clock signal at the input of the divider, D
CHANNEL
t
t
/T
/T
PO = 0
PO = 1
PO = 2
SH = 0
SH = 0
SH = 0
X
X
X
= Φ
Figure 42. Effect of Coarse Phase Offset (or Delay)
X.1
× D
0
1
X.2
Tx
2
or up to 1024. Both of the dividers also
3
X
1 × Tx
2 × Tx
4
5
6
7
8
9 10 11 12 13 14 15
X
).
X
Rev. 0 | Page 38 of 76
(in
Table 34. Setting Division (D
Divider
3
4
Note that the value stored in the register equals the number of
cycles minus one. For example, 0x199[7:4] = 0001b equals two
low cycles (M = 2) for Divider 3.1.
Channel Frequency Division (Divider 3 and Divider 4)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).
When both X.1 and X.2 are bypassed, D
When only X.2 is bypassed, D
When both X.1 and X.2 are not bypassed, D
(N
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (D
If only one divider is needed when using Divider 3 and Divider 4,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)); however,
with these channel dividers, the number of possible
configurations is more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
•
•
•
•
X.2
Number of Low Cycles = M
Number of High Cycles = N
An even D
cycles).
An odd D
low cycles must be one greater than the number of high
cycles).
If only one divider is bypassed, it must be the second
divider, X.2.
If only one divider has an even divide by, it must be the
second divider, X.2.
3.1
3.2
4.1
4.2
+ M
X.2
M
0x199[7:4]
0x19B[7:4]
0x19E[7:4]
0x1A0[7:4]
+ 2).
X.Y
X.Y
must be set as M
must be set as M
N
0x199[3:0]
0x19B[3:0]
0x19E[3:0]
0x1A0[3:0]
X
X
) for Divider 3 and Divider 4
= (N
X.Y
X.Y
X.Y
+ 1
+ 1
X.Y
X.1
= N
= N
X.1
+ M
X
Bypass
0x19C[4]
0x19C[5]
0x1A1[4]
0x1A1[5]
× D
X.Y
= 1 × 1 = 1.
X.Y
X
X.1
= (N
+ 1 (the number of
X.2
(low cycles = high
+ 2) × 1.
) can be realized.
X.1
+ M
DCCOFF
0x19D[0]
0x19D[0]
0x1A2[0]
0x1A2[0]
X.1
+ 2) ×