AD9516-5BCPZ Analog Devices Inc, AD9516-5BCPZ Datasheet - Page 57

• Manufacturer Part Number: AD9516-5BCPZ
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
017
018
018
018
019
019
019
[1:0] Antibacklash
[6:5] Lock detect
[4]
[3]
[7:6] R, A, B
[5:3] R path delay [5:3] R Path Delay, see Table 2 (default: 0x0).
[2:0] N path delay [2:0] N Path Delay, see Table 2 (default: 0x0).
pulse width
counter
Digital lock
detect
window
Disable
digital
lock detect
counters
SYNC pin
reset
[7]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[1]
0
0
1
1
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates
a locked condition.
[6]
0
0
1
1
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the
digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
[4] = 0; high range (default).
[4] = 1; low range.
Digital lock detect operation.
[3] = 0; normal lock detect operation (default).
[3] = 1; disable lock detect.
[7]
0
0
1
1
Description
[0]
0
1
0
1
[5]
0
1
0
1
[6]
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[6]
0
1
0
1
[5] [4]
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Antibacklash Pulse Width (ns)
2.9 (default)
1.3
6.0
2.9
PFD Cycles to Determine Lock
5 (default)
16
64
255
Action
Do nothing on SYNC (default).
Asynchronous reset.
Synchronous reset.
Do nothing on SYNC.
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
[3]
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
[2]
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 0 | Page 57 of 76
Level or
Dynamic
Signal
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Signal at STATUS Pin
LD pin comparator output (active high).
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in
differential mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (Status of REF2 frequency).
(DLD) AND (Status of selected reference) AND (Status of CLK) .
Status of CLK Frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD) (active low).
Holdover active (active low).
LD pin comparator output (active low).
AD9516-5