AD9518-1BCPZ-REEL7 Analog Devices Inc, AD9518-1BCPZ-REEL7 Datasheet - Page 5
![IC,Six Distributed-Output Clock Driver,LLCC,48PIN,PLASTIC](/photos/6/50/65022/cp-48-8_sml.jpg)
AD9518-1BCPZ-REEL7
Manufacturer Part Number
AD9518-1BCPZ-REEL7
Description
IC,Six Distributed-Output Clock Driver,LLCC,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9518-1ABCPZ-RL7.pdf
(64 pages)
Specifications of AD9518-1BCPZ-REEL7
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
1:6
Differential - Input:output
Yes/Yes
Frequency - Max
2.65GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.65GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
48
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9518-1/PCBZ - BOARD EVAL FOR AD9518-1
Lead Free Status / Rohs Status
Compliant
Parameter
CHARGE PUMP (CP)
PRESCALER (PART OF N DIVIDER)
PLL DIVIDER DELAYS
NOISE CHARACTERISTICS
PLL DIGITAL LOCK DETECT WINDOW
1
2
REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
I
I
Sink-and-Source Current Matching
I
I
Prescaler Input Frequency
Prescaler Output Frequency
000
001
010
011
100
101
110
111
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
PLL Figure of Merit (FOM)
Required to Lock (Coincidence of Edges)
To Unlock After Lock (Hysteresis)
CP
CP
CP
CP
High Value
Low Value
Absolute Accuracy
CP
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Sink/Source
High Impedance Mode Leakage
vs. CP
vs. Temperature
RSET
Range
V
2
2
Min
Typ
4.8
0.60
2.5
2.7/10
1
2
1.5
2
Off
330
440
550
660
770
880
990
−165
−162
−151
−143
−220
3.5
7.5
3.5
7
15
11
Max
300
600
900
600
1000
2400
3000
3000
300
Rev. A | Page 5 of 64
Unit
mA
mA
%
kΩ
nA
%
%
%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
Programmable
With CP
CP
0.5 < CP
0.5 < CP
CP
A, B counter input frequency (prescaler input frequency
divided by P)
See Table 44, Register 0x019: R, Bits[5:3]; N, Bits[2:0]
The PLL in-band phase noise floor is estimated by measuring
the in-band phase noise at the output of the VCO and
subtracting 20 log(N) (where N is the value of the N divider)
Reference slew rate > 0.25 V/ns; FOM +10 log(f
an approximation of the PFD/CP in-band phase noise (in the
flat region) inside the PLL loop bandwidth; when running closed
loop, the phase noise, as observed at the VCO output, is
increased by 20 log(N)
Signal available at LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
V
V
= V
= V
CP
CP
RSET
V
V
/2 V
/2 V
< V
< V
= 5.1 kΩ
CP
CP
− 0.5 V
− 0.5 V
PFD
AD9518-1
) is