AD9520-0/PCBZ Analog Devices Inc, AD9520-0/PCBZ Datasheet - Page 14

• Manufacturer Part Number: AD9520-0/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-0/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-0
SERIAL CONTROL PORT—I²C MODE
Table 14.
Parameter
SDA, SCL (WHEN INPUTTING DATA)
SDA (WHEN OUTPUTTING DATA)
TIMING
1
According to the original I
falling edge.
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between 0.1 × VS
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be Suppressed by the
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIH
Clock Rate (SCL, f
Bus Free Time Between a Stop and Start Condition, t
Setup Time for a Repeated Start Condition, t
Hold Time (Repeated) Start Condition (After This Period,
Setup Time for Stop Condition, t
Low Period of the SCL Clock, t
High Period of the SCL Clock, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Capacitive Load for Each Bus Line, C
and 0.9 × VS
Input Filter, t
Capacitance from 10 pF to 400 pF
the First Clock Pulse Is Generated), t
SPIKE
I2C
HLD; DAT
SET; DAT
)
FALL
2
RISE
C specification, an I
MIN
to VIL
LOW
HIGH
SET; STP
MAX
b
2
C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
with a Bus
HLD; STR
SET; STR
IDLE
Rev. 0 | Page 14 of 84
Min
0.7 × VS
−10
0.015 × VS
20 + 0.1 C
1.3
0.6
0.6
0.6
1.3
0.6
20 + 0.1 C
20 + 0.1 C
120
140
b
b
b
Typ
Max
0.3 × VS
+10
50
0.4
250
400
300
300
880
400
Unit
ns
ns
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
pF
V
V
μA
V
V
Test Conditions/Comments
C
Note that all I
referred to VIH
VIL
This is a minor deviation from the
original I²C specification of 100 ns
minimum
This is a minor deviation from the
original I²C specification of 0 ns
minimum
b
= capacitance of one bus line in pF
MAX
levels (0.7 × VS)
1
2
C timing values are
MIN
(0.3 × VS) and