AD9520-0/PCBZ Analog Devices Inc, AD9520-0/PCBZ Datasheet - Page 49

• Manufacturer Part Number: AD9520-0/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-0/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LVPECL Output Drivers
The LVPECL differential voltage (V
~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to
Register 0x0FB. The LVPECL outputs have dedicated pins for
power supply (VS_DRV), allowing a separate power supply to
be used. VS_DRV can be from 2.5 V or 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have two power-down
modes: total power-down and safe power-down.
In total power-down mode, all output drivers are shut off
simultaneously. This mode must not be used if there is an
external voltage bias network (such as Thevenin equivalent
termination) on the output pins that will cause a dc voltage to
appear at the powered down outputs. However, total power-
down mode is allowed when the LVPECL drivers are terminated
using only pull-down resistors. The total power-down mode is
activated by setting 0x230[1].
The primary power-down mode is the safe power-down mode.
This mode continues to protect the output devices while
powered down. There are three ways to activate safe power-
down mode: individually set the power-down bit for each
driver, power down an individual output channel (all of the
drivers associated with that channel are powered down
automatically), and activate sleep mode.
SW1B
Figure 53. LVPECL Output Simplified Equivalent Circuit
200Ω
R2
SW1A
200Ω
R1
SW2
4.4mA
N2
N1
QN2
QN1
OD
) is selectable (from
OUT
OUT
Rev. 0 | Page 49 of 84
CMOS Output Drivers
The user can also individually configure each LVPECL output
as a pair of CMOS outputs, which provides up to 24 CMOS
outputs. When an output is configured as CMOS, CMOS
Output A and CMOS Output B are automatically turned on.
For a given differential pair, either CMOS Output A or Output
B can be turned on or off independently. The user can also
select the relative polarity of the CMOS outputs for any
combination of inverting and noninverting (see Register 0x0F0
to Register 0x0FB).
The user can power down each CMOS output as needed to save
power. The CMOS output power-down is individually controlled
by the enable CMOS output register (0x0F0[6:5] to 0x0FB[6:5]).
The CMOS driver is in tristate when it is powered down.
RESET MODES
The AD9520 has a power-on reset (POR) and several other
ways to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when
VS reaches ~2.6 V (<2.8 V) and restores the chip either to the
setting stored in EEPROM (with the EEPROM pin = 1) or to
the on-chip setting (with the EEPROM pin = 0). At power-on,
the AD9520 also executes a SYNC operation, which brings the
outputs into phase alignment according to the default settings.
It takes ~70 ms for the outputs to begin toggling after the
power-on reset pulse signal is internally generated.
Hardware Reset via the RESET Pin
RESET , a hard reset (an asynchronous hard reset is executed by
briefly pulling RESET low), restores the chip either to the setting
stored in EEPROM (the EEPROM pin = 1) or to the on-chip
setting (the EEPROM pin = 0). A hard reset also executes a
SYNC operation, which brings the outputs into phase alignment
according to the default settings. When EEPROM is inactive
(the EEPROM pin = 0), it takes ~2 μs for the outputs to begin
toggling after RESET is issued. When EEPROM is active (the
EEPROM pin = 1), it takes ~20 ms for the outputs to toggle after
RESET is brought high.
Figure 54. CMOS Equivalent Output Circuit
VS_DRV
OUT1/
OUT1
AD9520-0