AD9520-5BCPZ-REEL7 Analog Devices Inc, AD9520-5BCPZ-REEL7 Datasheet - Page 12
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AD9520-5BCPZ-REEL7
Manufacturer Part Number
AD9520-5BCPZ-REEL7
Description
12/24-Output Clock Generator
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9520-5BCPZ.pdf
(80 pages)
Specifications of AD9520-5BCPZ-REEL7
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.6GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9520-5
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 9.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
SERIAL CONTROL PORT—SPI MODE
Table 10.
Parameter
CS (INPUT)
SCLK (INPUT) IN SPI MODE
SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE)
SDIO, SDO (OUTPUTS)
TIMING
CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz;
CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz;
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz;
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, t
CS Minimum Pulse Width High, t
Channel Divider = 2; Duty-Cycle Correction = Off
Bypass Channel Divider; Duty-Cycle Correction = On
Bypass Channel Divider; Duty-Cycle Correction = Off
Channel Divider = 8; Duty-Cycle Correction = Off
LOW
HIGH
DH
SCLK
DS
)
S
, t
DV
C
PWH
Min
2.0
2.0
2.0
2.7
16
16
4
0
2
3
Typ
−110
2
110
2
1
1
2
Min
Rev. 0 | Page 12 of 80
Typ
230
215
326
362
Max
0.8
3
0.8
1
0.8
0.4
25
11
Max
Unit
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Unit
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
The minus sign indicates that current is flowing out of
the AD9520, which is due to the internal pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor in SPI
mode, but not in I
Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
(broadband jitter)
Calculated from SNR of ADC method
(broadband jitter)
Distribution section only; does not include PLL;
uses rising edge of clock signal
Calculated from SNR of ADC method
(broadband jitter)
Calculated from SNR of ADC method
(broadband jitter)
2
C mode