AD9627BCPZ-150 Analog Devices Inc, AD9627BCPZ-150 Datasheet - Page 31

• Manufacturer Part Number: AD9627BCPZ-150
• Description: IC,A/D CONVERTER,DUAL,12-BIT,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9627BCPZ-150

• Number Of Bits: 12
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 890mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9627-150EBZ - BOARD EVAL FOR AD9627-150AD9627-125EBZ - IC A/D 12BIT 125MSPS DL EVAL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER DISSIPATION AND STANDBY MODE
As shown in Figure 63 through Figure 66, the power dissipated
by the AD9627 is proportional to its sample rate. In CMOS
output mode, the digital power dissipation is determined
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (I
where N is the number of output bits (26, in the case of the
AD9627, with the fast detect output pins disabled).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 63 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
1.25
1.00
0.75
0.50
0.25
1.25
1.00
0.75
0.50
0.25
I
DRVDD
0
0
0
0
Figure 63. AD9627-150 Power and Current vs. Sample Rate
Figure 64. AD9627-125 Power and Current vs. Sample Rate
= V
CLK
25
DRVDD
25
TOTAL POWER
/2. In practice, the DRVDD current is
TOTAL POWER
I
AVDD
× C
I
DVDD
50
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
LOAD
I
DVDD
50
× f
75
CLK
I
AVDD
× N
DRVDD
75
100
) can be calculated as
I
DRVDD
100
125
I
DRVDD
150
125
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
Rev. B | Page 31 of 76
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9627 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD9627 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section for more details.
1.00
0.75
0.50
0.25
0.75
0.50
0.25
0
0
0
0
Figure 65. AD9627-105 Power and Current vs. Sample Rate
Figure 66. AD9627-80 Power and Current vs. Sample Rate
I
I
DVDD
DVDD
25
20
TOTAL POWER
I
AVDD
I
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
AVDD
TOTAL POWER
50
40
I
DRVDD
75
60
I
DRVDD
100
AD9627
80
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0