AD9627BCPZ-150 Analog Devices Inc, AD9627BCPZ-150 Datasheet - Page 39

• Manufacturer Part Number: AD9627BCPZ-150
• Description: IC,A/D CONVERTER,DUAL,12-BIT,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9627BCPZ-150

• Number Of Bits: 12
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 890mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9627-150EBZ - BOARD EVAL FOR AD9627-150AD9627-125EBZ - IC A/D 12BIT 125MSPS DL EVAL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9627 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9627.
Various output test options are also provided to place predictable
values on the outputs of the AD9627.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9627 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value for Channel A or
Channel B is placed in Register 0x24 and Register 0x25. If one
channel is chosen, its BIST signature is written to the two registers.
If both channels are chosen, the results from Channel A are placed
in the BIST signature registers.
Rev. B | Page 39 of 76
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 25. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see
Application Note AN-877, Interfacing to High Speed ADCs via SPI.
AD9627