AD9739-EBZ Analog Devices Inc, AD9739-EBZ Datasheet - Page 25

• Manufacturer Part Number: AD9739-EBZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739-EBZ

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 2.5G
• Data Interface: SPI™
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9739
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The AD9739 is a 14-bit DAC that operates at an update rate of
up to 2.5 GSPS. Due to internal timing requirements, the
minimum allowable sample rate is 800 MSPS. Input data is
sampled through two 14-bit LVDS ports that are internally
multiplexed. Each port has its own data inputs, but both ports
share a common DCI input. The LVDS inputs meet the IEEE-
1596 reduced swing specification with the exception of input
hysteresis, which is not guaranteed over all process corners.
Each DCI input runs at one-quarter the input data rate in a
double data rate (DDR) format. Each edge of DCI is used to
transfer data into the AD9739.
The DACCLK_N/DACCLK_P inputs directly drive the DAC
core to minimize clock jitter. The DACCLK signal is divided by
4 then output as the DCO for each port. The DCO signal can be
used to clock the data source. The DAC expects DDR LVDS
data (DB0[13:0], DB1[13:0]), with each channel aligned with
the single DDR data input clock (DCI).
Control of the AD9739 functions is via a serial peripheral
interface (SPI).
SERIAL PERIPHERAL INTERFACE
The AD9739 serial port is a flexible, synchronous serial
communications port, allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer formats,
including the Motorola® SPI and the Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9739. Most significant bit first (MSB-first) or least
significant bit first (LSB-first) transfer formats are supported.
The AD9739 serial interface port can be configured as a single
pin I/O (SDIO) or two unidirectional pins for input/output
(SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9739.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9739 coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9739
serial port controller with information about the data transfer
cycle, which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines whether the upcoming data transfer is
read or write and the starting register address for the first byte
of the data transfer. The first eight SCLK rising edges of each
communication cycle are used to write the instruction byte into
the AD9739.
SCLK (PIN H13)
SDIO (PIN G14)
SDO (PIN H14)
CS
(PIN G13)
Figure 73. AD9739 SPI Port
AD9739
SPI PORT
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The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9739
and the system controller. Phase 2 of the communication cycle
is a transfer of one byte only. Single-byte data transfers are
useful to reduce CPU overhead when register access requires
one byte only. Registers change immediately upon writing to the
last bit of each transfer byte. CS (chip select) can be raised after
each sequence of eight bits (except the last byte) to stall the bus.
The serial transfer resumes when CS is lowered. Stalling on
nonbyte boundaries resets the SPI.
INSTRUCTION MODE (8-BIT INSTRUCTION)
The instruction byte is shown in the following table.
MSB
I7
R/W
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation, the data transfer cycle. A6 to A0 (Bit 6 through Bit 0
of the instruction byte) determine which register is accessed
during the data transfer portion of the communications cycle.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9739 and to run the internal state machines. The maximum
frequency of SCLK is 20 MHz. All data input to the AD9739 is
registered on the rising edge of SCLK. All data is driven out of
the AD9739 on the rising edge of SCLK.
CS —Chip Select
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
SDIO—Serial Data I/O
Data is always written into the AD9739 on this pin. However,
this pin can be used as a bidirectional data line. The configu-
ration of this pin is controlled by SDIO_DIR at Register 0x00,
Bit 7. The default is Logic 0, which configures the SDIO pin as
unidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9739 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
I6
A6
I5
A5
I4
A4
I3
A3
I2
A2
I1
A1
AD9739
LSB
I0
A0