AD9739-R2-EBZ Analog Devices Inc, AD9739-R2-EBZ Datasheet - Page 33

• Manufacturer Part Number: AD9739-R2-EBZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739-R2-EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 24. LVDS Receiver Status Registers (Register 0x19, Register 0x1A, Register 0x1B, Register 0x1C, Register 0x1D,
Register 0x1E, Register 0x1F, Register 0x20, Register 0x21)
Register
Name
LVDS_
REC_STAT1
LVDS_
REC_STAT2
LVDS_
REC_STAT3
LVDS_
REC_STAT4
LVDS_
REC_STAT5
LVDS_
REC_STAT6
LVDS_
REC_STAT7
LVDS_
REC_STAT8
LVDS_
REC_STAT9
1
Table 25. LVDS Receiver Status Register Bit Descriptions
Bit Name
SMP_DEL[9:0]
SMP_FINE_DEL[3:0]
SYNCOUTPH[1:0]
CLKDIVPH[1:0]
DCI_DEL[9:0]
FINE_DEL_PRE[3:0]
FINE_DEL_PST[3:0]
SYNCO_DEL[6:0]
SYNCSH_DEL[8:0]
SYNC_TRK_ON
SYNC_INIT_ON
SYNC_LST_LCK
SYNC_LCK
RCVR_TRK_ON
The two-digit number is the decimal representation of the address.
Address
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
1
25
26
27
28
29
30
31
32
33
Read/Write
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Bit 7
SMP_DEL[1]
SMP_DEL[9]
DCI_DEL[1]
DCI_DEL[9]
FINE_DEL_
PST[3]
N/A
SYNCSH_
DEL[0]
SYNCSH_
DEL[8]
SYNC_TRK_
ON
Description
Readback of the present SMP_DEL value. In tracking mode, it represents the
current valid SMP_DEL setting. In manual mode, it is a readback of the value
written to SMP_DEL[9:0] in Register 17 and Register 18.
Readback of the sample fine delay line value (this is the same as FINE_MID_DEL).
Readback of the present SYNC_OUT phase selection.
Readback of the present CLK divider phase rotation.
Readback of the present DCI_DEL value. In tracking mode, it represents the
current valid DCI_DEL setting. In manual mode, it is a readback of the value
written to DCI_DEL[9:0] in Register 13 and Register 14.
Present fine delay setting for the pre DCI window search delay line.
Present fine delay setting for the post DCI window search delay line.
Readback of the present SYNCO_DEL value. In tracking mode, it represents the
current value of the SYNCO_DEL setting. In manual mode, it is a readback of the
value written to SYNCO_DEL[6:0] in Register 16.
Readback of the present SYNCSH_DEL value. In tracking mode, it represents the
current value of the SYNCSH_DEL setting. In manual mode, it is a readback of the
value written to SYNCSH_DEL[8:0] in Register 17 and Register 18.
0: with the sync controller enabled, tracking mode has not been established.
1: with the sync controller enabled, tracking mode has been established.
1: indicates that the sync controller is in initialize mode.
0: sync lock has not been lost.
1: sync lock has been lost at some point.
0: the sync controller is not locked.
1: the sync controller is locked.
0: with the receiver controller enabled, tracking mode has not been established.
1: with the receiver controller enabled, tracking mode has been established.
Bit 6
SMP_DEL[0]
SMP_DEL[8]
DCI_DEL[0]
DCI_DEL[8]
FINE_DEL_
PST[2]
SYNCO_
DEL[6]
N/A
SYNCSH_
DEL[7]
SYNC_INIT_
ON
Bit 5
N/A
SMP_DEL[7]
N/A
DCI_DEL[7]
FINE_DEL_
PST[1]
SYNCO_
DEL[5]
N/A
SYNCSH_
DEL[6]
SYNC_LST
_LCK
Rev. 0 | Page 33 of 56
Bit 4
N/A
SMP_DEL[6]
N/A
DCI_DEL[6]
FINE_DEL_
PST[0]
SYNCO_
DEL[4]
N/A
SYNCSH_
DEL[5]
SYNC_LCK
Bit 3
SMP_FINE
_DEL[3]
SMP_DEL[5]
SYNCOUT
PH[1]
DCI_DEL[5]
FINE_DEL_
PRE[3]
SYNCO_
DEL[3]
N/A
SYNCSH_
DEL[4]
RCVR_TRK_
ON
Bit 2
SMP_FINE
_DEL[2]
SMP_DEL[4]
SYNCOUT
PH[0]
DCI_DEL[4]
FINE_DEL_
PRE[2]
SYNCO_
DEL[2]
N/A
SYNCSH_
DEL[3]
RCVR_FE_
ON
Bit 1
SMP_FINE
_DEL[1]
SMP_DEL[3]
CLKDIV
PH[1]
DCI_DEL[3]
FINE_DEL_
PRE[1]
SYNCO_
DEL[1]
N/A
SYNCSH_
DEL[2]
RCVR_LST_
LCK
Reset Value for
Write Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD9739
Bit 0
SMP_FINE
_DEL[0]
SMP_DEL[2]
CLKDIV
PH[0]
DCI_DEL[2]
FINE_DEL_
PRE[0]
SYNCO_
DEL[0]
N/A
SYNCSH_
DEL[1]
RCVR_LCK