AD9739-R2-EBZ Analog Devices Inc, AD9739-R2-EBZ Datasheet - Page 37

• Manufacturer Part Number: AD9739-R2-EBZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739-R2-EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
ANALOG MODES OF OPERATION
The AD9739 uses the quad-switch architecture shown in
Figure 80, which can be configured to operate in one of the
following three modes via the serial peripheral interface:
normal mode, RZ mode, and analog mix mode.
The quad-switch architecture masks the code-dependent glitches
that occur in a conventional two-switch DAC. Figure 81 shows
the waveforms for a conventional DAC and the quad-switch
DAC. In the two-switch architecture, when a switch transition
occurs and D
if D
and no glitches occur. This code-dependent glitching causes an
increased amount of distortion in the DAC. In quad-switch
architecture (no matter what the codes are), there are always
two switches transitioning at each half clock cycle, thus
eliminating the code-dependent glitches but, in the process,
creating a constant glitch at 2 × DACCLK_x.
The quad-switch architecture can also be easily configured to
perform an analog mix or return-to-zero (RZ) function. In the
mix mode, the output is effectively chopped at twice the DAC
sample rate. This has the effect of reducing the power of the
fundamental signal while increasing the power of the images
centered around the DAC sample rate, thus improving the
dynamic range of the higher frequency signals.
The RZ mode is similar to the analog mix mode, except that the
intermediate data samples are replaced with midscale values
rather than inverting. Figure 82 shows the DAC waveforms for
both the mix mode and RZ modes.
(NORMAL MODE)
DACCLK_x
DBx[13:0]
FOUR-SWITCH
1
TWO-SWITCH
DAC OUTPUT
DAC OUTPUT
and D
DACCLK_x
Figure 81. Two-Switch and Quad-Switch DAC Waveforms
INPUT
DATA
2
happen to be at the same state, the switch transitions,
Figure 80. AD9739 Quad-Switch Architecture
1
LATCHES
and D
CLK
D
D
D
1
1
1
D
2
D
D
2
V
V
V
V
are in different states, a glitch occurs. But,
2
2
G
G
G
G
1
2
3
4
D
D
D
3
3
3
D
V
D
D
4
G
4
4
1
D
I
OUT
D
D
5
5
5
P
D
D
D
6
6
6
D
V
D
D
G
7
V
7
7
2
DD
D
V
D
D
G
8
8
8
3
D
D
D
9
9
9
I
OUT
D
D
D
10
10
10
N
V
G
t
t
4
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This ability to change modes in the AD9739 makes it suitable
for both CMTS and UMTS applications. The user can place a
carrier anywhere in the first three Nyquist zones, depending on
the operating mode selected. Switching between the analog
modes reshapes the sinc roll-off inherent at the DAC output.
The performance and maximum amplitude in all three Nyquist
zones are impacted by this sinc roll-off, depending on where the
carrier is placed, as shown in Figure 83.
LVDS DATA PORT INTERFACE
The AD9739 contains two parallel LVDS input ports consisting of
14 differential LVDS signals DB[13:0]. In addition to the LVDS
data lines, there are four other LVDS signals: SYNC_IN_x, SYNC_
OUT_x, DATACLOCK_OUT (DCO_x), and DATACLK_IN
(DCI_x). A top level diagram of the data receiver and controller
is shown in Figure 84.
The timing optimization for both ports is performed by using a
single DCI, and clocking of the external digital signal generator
(such as FPGA and ASIC) is done using a single DCO.
FOUR-SWITCH
FOUR-SWITCH
(
f
DAC OUTPUT
DAC OUTPUT
ZERO MODE)
S
(RETURN TO
–10
–15
–20
–25
–30
–35
MIX MODE)
DACCLK_x
–5
0
0FS
RZ MODE
INPUT
Figure 83. Sinc Roll-Off for Each Analog Operating Mode
DATA
NYQUIST ZONE
0.25FS
Figure 82. Mix Mode and RZ DAC Waveforms
FIRST
D
D
1
D
1
–D
1
D
1
D
2
D
2
–D
2
0.50FS
D
2
D
3
D
3
–D
FREQUENCY (Hz)
3
NYQUIST ZONE
D
3
D
4
MIX MODE
D
4
SECOND
–D
4
0.75FS
D
4
D
5
D
5
–D
5
5
D
D
6
D
6
NORMAL
–D
6
1.00FS
MODE
D
6
D
7
D
7
–D
7
NYQUIST ZONE
D
7
D
8
8
D
–D
8
1.25FS
THIRD
D
8
D
9
9
D
–D
9
D
9
D
10
10
D
–D
AD9739
10
1.50FS
10
t
t