AD9739BBCZ Analog Devices Inc, AD9739BBCZ Datasheet - Page 39
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AD9739BBCZ
Manufacturer Part Number
AD9739BBCZ
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBCZ
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9739BBCZ
Manufacturer:
EXAR
Quantity:
101
Company:
Part Number:
AD9739BBCZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD9739BBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
CLOCKING THE AD9739
To provide the required signal swing for the internal clock
receiver of the AD9739, it is necessary to use an external clock
buffer chip to drive the DACCLK_P and DACCLK_N inputs.
The recommended clock buffer for this application is the
ADCLK914. This is an ultrafast clock buffer capable of
providing 1.9 V out of each side into a 50 Ω load terminated to
VCC (3.3 V) for a total differential swing of 3.8 V. This buffer
also provides very low jitter, 100 FS random jitter, which is
important for optimal ac performance in the AD9739.
A functional block diagram of the ADCLK914 is shown in
Figure 85. Figure 86 shows the recommended schematic for the
ADCLK914/AD9739 interface. See the ADCLK914 data sheet
for more information.
2
3
GND
J3
4
5
1
R15
49.9Ω
GND
0.01µF
0.01µF
C81
C82
GND
GND
1
2
3
4
Figure 86. Recommended ADLCK914/AD9739 Interface Circuit
D
D
NC
NC
C83
0.01µF
GND
NC
NC
Q
Q
U3
GEN_QFN16_3X3_PAD
ADCLK914
12
11
10
9
Rev. 0 | Page 39 of 56
VCC33
VCC33
1_5X1_5
For optimal ac performance out of the AD9739, the recommended
minimum differential peak-to-peak voltage is approximately
1.4 VPP. The maximum allowable clock frequency is 2.5 GSPS and,
due to internal timing requirements for the part, the minimum
allowable clock frequency is 800 MSPS.
V
REF
ADCLK914 SUPPLY DECOUPLING
V
C31
0.1µF
C0402
GND
D
D
T
R13
49.9Ω
50Ω
C32
0.01µF
C0402
GND
Figure 85. ADCLK914 Functional Block Diagram
50Ω
R14
49.9Ω
C33
0.1µF
C0402
GND
VCC33
2400pF
2400pF
C102
V
V
C99
CC
EE
C34
0.01µF
C0402
GND
VCC33
ADCLK914
R17
100Ω
R0402
CLKP
CLKN
Q
Q
AD9739
50Ω
50Ω