AD9739BBCZ Analog Devices Inc, AD9739BBCZ Datasheet - Page 52

• Manufacturer Part Number: AD9739BBCZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCZ

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9739
6.
7.
Table 44.
Register
LVDS_REC_
CNT1
LVDS_REC_
CNT2
LVDS_REC_
CNT3
LVDS_REC_
CNT4
LVDS_REC_
CNT5
LVDS_REC_
CNT6
LVDS_REC_
CNT7
LVDS_REC_
CNT8
LVDS_REC_
CNT9
1
To verify that the LVDS controller is locked, tracking, and
sampling on the correct phase, the following bits must be read
back:
•
•
•
•
The two-digit number is the decimal representation of the address.
To verify that the sync controller is locked and tracking, the following bits must be read back:
•
•
•
•
•
Load the desired data pattern.
Enable the LVDS controller and ensure that it locks. If the synchronization controller is being used, keep the values from Step 5 in
the registers and add the values in Table 44.
Register 0x21, Bit 0 (RCVR_LCK)—If the controller is
locked, this bit reads back a value of 1.
Register 0x21, Bit 3 (RCVR_TRK_ON)—If the controller is
tracking this bit reads back a value of 1.
Register 0x0C, Bit 5 (DCI_PHS3)—If the controller is
locked on the correct phase and the data is sampling
correctly, this bit reads back a value of 0.
Register 0x0C, Bit 4 (DCI_PHS1)—If the controller is
locked on the correct phase and the data is sampling
correctly, this bit reads back a value of 1.
Register 0x21, Bit 4 (SYNC_LCK)—If the controller is locked, this bit reads back a value of 1. This is a value of 1 for the master
part only. If the part is set up as a slave, this bit reads back 0.
Register 0x21, Bit 7 (SYNC_TRK_ON)—If the controller is tracking, this bit reads back a value of 1. This is a value of 1 for the
master part only. If the part is set up as a slave, this bit reads back 0.
Register 0x21, Bit 5 (SYNC_LST_LCK)—If the controller is locked, this bit reads back a value of 0. If the controller comes out of
lock, this bit reads back a value of 1. This bit is valid for the master part only.
Register 0x0D, Bit 4 (SYNC_SAMP0)—If the controller is locked and the SYNC_IN signal is positioned correctly, this bit reads
back a value of 0. This state is valid for both the master and slave parts.
Register 0x0D, Bit 5 (SYNC_SAMP1)—If the controller is locked and the SYNC_IN signal is positioned correctly, this bit reads
back a value of 1. This state is valid for both the master and slave parts.
Address
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
16
17
18
19
20
21
22
23
24
1
Bit 7
SYNC_
FLG_RST
(0)
SMP_DEL
[1] (1)
SMP_DEL
[9] (0)
DCI_DEL
[3] (0)
CLKDIVPH
[1]] (0)
SYNC_
GAIN[1](0)
N/A
SYNCSH_
DEL[0] (0)
SYNCSH_
DEL[8] (0)
Bit 6
SYNC_
LOOP_ON
(0)
SMP_DEL
[0] (0)
SMP_DEL
[8] (0)
DCI_DEL
[2] (1)
CLKDIVPH
[0] (0)
SYNC_
GAIN[0](1)
SYNCO_
DEL[6] (0)
N/A
SYNCSH_
DEL[7] (0)
Bit 5
SYNC_
MST/SLV
(0)
FINE_DEL_
MID[3] (0)
SMP_DEL
[7] (1)
DCI_DEL
[1] (1)
DCI_DEL[9]
(0)
SYNCOUT_
PH[1](0)
SYNCO_
DEL[5] (0)
N/A
SYNCSH_
DEL[6] (0)
Rev. 0 | Page 52 of 56
Bit 4
SYNC_
CNT_ENA
(0)
FINE_DEL_
MID[2] (1)
SMP_DEL
[6] (1)
DCI_DEL
[0] (0)
DCI_DEL
[8] (0)
SYNCOUT_
PH[0](0)
SYNCO_
DEL[4] (0)
N/A
SYNCSH_
DEL[5] (0)
•
•
Bit 3
N/A
FINE_DEL
_MID[1]
(1)
SMP_DEL
[5] (1)
FINE_DEL
_SKW[3]
(0)
DCI_DEL
[7] (1)
LCKTHR[3]
(0)
SYNCO_
DEL[3] (0)
N/A
SYNCSH_
DEL[4] (0)
Register 0x19, Bits [7:6] and Register 0x1A, Bits[7:0]
(SMP_DEL[9:0])—This corresponds to the present sample
delay value that the controller locked to. Continuous
readback of these bits shows how the sample delay value
changes to maintain proper sampling in the presence of
temperature shifts in the system.
Register 0x1B, Bits[7:6] and Register 0x1C, Bits[7:0]
(DCI_DEL[9:0])—This corresponds to the present DCI
delay value that the controller locked to. Continuous
readback of these bits shows how the DCI value changes to
maintain proper sampling in the presence of temperature
shifts in the system.
Bit 2
RCVR_
FLG_RST
(0)
FINE_DEL
_MID[0]
(1)
SMP_DEL
[4] (0)
FINE_DEL
_SKW[2]
(0)
DCI_DEL
[6] (0)
LCKTHR[2]
(0)
SYNCO_
DEL[2] (0)
N/A
SYNCSH_
DEL[3] (0)
Bit 1
RCVR_
LOOP_
ON (1)
RCVR_
GAIN [1]
(0)
SMP_DEL
[3] (0)
FINE_DEL
_SKW[1]
(1)
DCI_DEL
[5] (1)
LCKTHR[1]
(1)
SYNCO_
DEL[1] (0)
N/A
SYNCSH_
DEL[2] (0)
Bit 0
RCVR_
CNT_ENA
(1)
RCVR_GAIN
[0] (1)
SMP_DEL
[2] (1)
FINE_DEL_
SKW[0] (0)
DCI_DEL
[4] (0)
LCKTHR[0]
(0)
SYNCO_
DEL[0] (0)
N/A
SYNCSH_
DEL[1] (0)
Recommended
Value
0x03 (no sync)
0x73 (sync
master)
0x53 (sync slave)
0x9D
0x29
0x62
0x0A
0x42
0x00
0x00
0x00