AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 25

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hex
Address
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
Read/Write,
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
7:0
7:0
7
6
5
4:3
2:0
7:0
7:3
2
1:0
7
6
5
4
Bits
Default
Value
***0 ****
**** 0***
**** *0**
**** **0*
**** ***0
0000 1000
0010 0000
0*** ****
*1** ****
**0* ****
***1 1***
**** *011
1111 1111
0111 1***
**** *0**
**** **00
*** ****
*0** ****
**1* ****
***1 ****
Register Name
Clamp Placement
Clamp Duration
Clamp and Offset
TestReg0
SOG Control
Power
Rev. 0 | Page 25 of 44
Number of clock periods that the clamp signal is actively clamping.
Must be set to 0xFF for proper operation.
Description
Clamp Source Select.
0 = Use the internal clamp generated from Hsync
1 = Use the external clamp signal
Red Clamp Select.
0 = Clamp the red channel to ground
1 = Clamp the red channel to midscale
Green Clamp Select.
0 = Clamp the green channel to ground
1 = Clamp the green channel to midscale
Blue Clamp Select.
0 = Clamp the blue channel to ground
1 = Clamp the blue channel to midscale
Must be set to 0 for proper operation.
Places the clamp signal an integer number of clock periods after
the trailing edge of the Hsync signal.
External Clamp Polarity Override.
0 = The chip selects the clamp polarity
1 = The polarity of the clamp signal is set by Reg. 0x1B, Bit 6
External Clamp Input Polarity. This bit is used only if Reg. 0x1B, Bit 7
is set to 1.
0 = Active low external clamp
1 = Active high external clamp
Auto-Offset Enable.
0 = Auto-offset is disabled
1 = Auto-offset is enabled (offsets become the desired clamp code)
Auto-Offset Update Frequency. This selects how often the auto-
offset circuit operates.
00 = every 3 clamps
01 = 48 clamps
10 = every 192 clamps
11 = every 3 Vsyncs
Must be written to default (011) for proper operation.
SOG Slicer Threshold. Sets the voltage level of the SOG slicer’s
comparator.
SOGOUT Polarity. Sets the polarity of the signal on the SOGOUT pin.
0 = Active low SOGOUT
1 = Active high SOGOUT
SOGOUT Select.
00 = Raw SOG from sync slicer (SOGIN0 or SOGIN1)
01 = Raw Hsync (HSYNC0 or HSYNC1)
10 = Regenerated sync from sync filter
11 = Filtered sync from sync filter
Channel Select Override.
0 = The chip determines which input channels to use
1 = The input channel selection is determined by Reg. 0x1E, Bit 6
Channel Select. Input channel select: this is used only if Reg. 0x1E,
Bit 7 is set to 1, or if syncs are present on both channels.
0 = Channel 0 syncs and data are selected
1 = Channel 1 syncs and data are selected
Programmable Bandwidth.
0 = Low analog input bandwidth (7 MHz)
1 = High analog input bandwidth
Power-Down Control Select.
0 = Manual power-down control
1 = Auto power-down control
AD9983A