AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 8

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9983A
Table 5. Pin Function Descriptions
Mnemonic
R
G
B
R
G
B
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
CLAMP
EXTCK/COAST
PWRDN
AIN0
AIN0
AIN1
AIN1
AIN0
AIN1
Function
Analog Input for the Red
Channel 0
Analog Input for the Green
Channel 0
Analog Input for the Blue
Channel 0
Analog Input for the Red
Channel 1
Analog Input for the Green
Channel 1
Analog Input for the Blue
Channel 1
Horizontal Sync Input
Channel 0
Horizontal Sync Input
Channel 1
Vertical Sync Input Channel 0
Vertical Sync Input Channel 1
Sync-on-Green Input
Channel 0
Sync-on-Green Input
Channel 1
External Clamp Input
(Optional)
External Clock
Coast Input to Clock
Generator (Optional)
Power-Down Control
Description
These are high impedance inputs that accept the red, green, and blue channel graphics
signals, respectively. The three channels are identical and can be used for any colors,
but colors are assigned for convenient reference. They accommodate input signals
ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to
support clamp operation. See Figure 4 and Figure 5.
These inputs receive a logic signal that establishes the horizontal timing reference and
provides the frequency reference for pixel clock generation. The logic sense of this pin
can be automatically determined by the chip or manually controlled by Serial Register
0x12, Bits[5:4] (Hsync polarity). Only the leading edge of Hsync is used by the PLL; the
trailing edge is used in clamp timing. When Hsync polarity = 0, the falling edge of
Hsync is used. When Hsync polarity = 1, the rising edge is active. The input includes a
Schmitt trigger for noise immunity.
These are the inputs for vertical sync and provide timing information for generation of
the field (odd/even) and internal Coast generation. The logic sense of this pin can be
automatically determined by the chip or manually controlled by Serial Register 0x14,
Bits[5:4] (Vsync polarity).
These inputs process signals with embedded sync, typically on the green channel. The
pin is connected to a high speed comparator with an internally generated threshold.
The threshold level can be programmed in 8 mV steps to any voltage between 8 mV
and 256 mV above the negative peak of the input signal. The default voltage threshold
is 128 mV. When connected to an ac-coupled graphics signal with embedded sync, it
produces a noninverting digital output on SOGOUT. This is usually a composite sync
signal, containing both vertical and horizontal sync information that must be separated
before passing the horizontal sync signal for Hsync processing. When not used, this
input should be left unconnected. For more details on this function and how it should
be configured, refer to the Sync-on-Green section.
This logic input can be used to define the time during which the input signal is
clamped to ground or midscale. It should be exercised when the reference dc level is
known to be present on the analog input channels, typically during the back porch of
the graphics signal. The CLAMP pin is enabled by setting the control bit clamp function
to 1, (Register 0x18, Bit 4; default is 0). When disabled, this pin is ignored and the clamp
timing is determined internally by counting a delay and duration from the trailing edge
of the Hsync input. The logic sense of this pin can be automatically determined by the
chip or controlled by clamp polarity Register 0x1B, Bits[7:6]. When not used, this pin
may be left unconnected (there is an internal pull-down resistor) and the clamp
function programmed to 0.
EXTCK allows the insertion of an external clock source rather than the internally
generated, PLL locked clock. EXTCK is enabled by programming Register 0x03, Bit 2 to 1.
This pin is shared with the Coast function, which does not affect EXTCK functionality.
COAST can be used to cause the pixel clock generator to stop synchronizing with Hsync
and continue producing a clock at its current frequency and phase. This is useful when
processing signals from sources that fail to produce Hsync pulses during the vertical
interval. The coast signal is generally not required for PC-generated signals. The logic
sense of this pin can be determined automatically or controlled by Coast polarity
(Register 0x18, Bits[7:6]). When not used and EXTCK not used, this pin may be grounded
and Coast polarity programmed to 1. Input Coast polarity defaults to1 at power-up. This
pin is shared with the EXTCK function, which does not affect coast functionality. For
more details on EXTCK, see the description in this section.
This pin can be used along with Register 0x1E, Bit 3 for manual power-down control.
If manual power-down control is selected (Register 0x1E, Bit 4) and this pin is not used,
it is recommended to set the pin polarity (Register 0x1E, Bit 2) to active high and
hardwire this pin to ground with a 10 kΩ resistor.
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