AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 30

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9983A
INPUT GAIN
0x05—Bits[6:0] Red Channel Gain Adjust
The 7-Bit Red Channel Gain Control. The AD9983A can
accommodate input signals with a full-scale range of between
0.5 V and 1.0 V p-p. Setting the red gain to 127 corresponds to
an input range of 1.0 V. A red gain of 0 establishes an input
range of 0.5 V. Note that increasing red gain results in the
picture having less contrast (the input signal uses fewer of the
available converter codes). Values written to this register do not
update until the following register (Register 0x06) has been
written to 0x00. The power-up default is 100 0000.
0x07—Bits[6:0] Green Channel Gain Adjust
The 7-Bit Green Channel Gain Control. See red channel gain adjust
above. Register update requires writing 0x00 to Register 0x08.
0x09—Bits[6:0] Blue Channel Gain Adjust
The 7-Bit Blue Channel Gain Control. See red channel gain adjust
above. Register update requires writing 0x00 to Register 0x0A.
INPUT OFFSET
0x0B—Bits[7:0] Red Channel Offset
The 8-Bit MSB of the Red Channel Offset Control. Along with
the LSB in the following register, there are 9 bits of dc offset
control in the red channel. The offset control shifts the analog
input, resulting in a change in brightness. Note that the function
of the offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).
If auto-offset is disabled, the lower 7 bits of the offset registers
(for the red channel Register 0x0B, Bits [5:0] plus Register 0x0C,
Bit 7) control the absolute offset added to the channel. The
offset control provides a ±63 LSBs of adjustment range, with 1 LSB
of offset corresponding to 1 LSB of output code.
If auto-offset is enabled, the 9-bit offset (comprised of the 8 bits
of the MSB register and Bit 7 of the following register) determines
the clamp target code. The 9-bit offset consists of 1 sign bit
plus 8 bits. If the register is programmed to 130d, then the
output code is equal to 130d at the end of the clamp period.
Incrementing the offset register setting by 1 LSB adds 1 LSB of
offset, regardless of the auto-offset setting. Values written to this
register are not updated until the LSB register (Register 0x0C)
has also been written.
0x0C—Bit[7] Red Channel Offset LSB
The LSB of the red channel offset control combines with the 8 bits
of MSB in the previous register to make 9 bits of offset control.
0x0D—Bits[7:0] Green Channel Offset
The 8-Bit Green Channel Offset Control. See red channel offset
(0x0B). Update of this register occurs only when Register 0x0E
is also written.
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0x0E—Bit[7] Green Channel Offset LSB
The LSB of the green channel offset control combines with the
8 bits of MSBs in the previous register to make 9 bits of offset
control.
0x0F—Bits[7:0] Blue Channel Offset
The 8-Bit Blue Channel Offset Control. See 0x0B—Bits[7:0]
Red Channel Offset. Update of this register occurs only when
Register 0x10 is also written.
0x10—Bit[7] Blue Channel Offset LSB
The LSB of the blue channel offset control combines with the
8 bits of MSB in the previous register to make 9 bits of offset
control.
HSYNC CONTROLS
0x11—Bits[7:0] Sync Separator Threshold
This register sets the threshold of the sync separator’s digital
comparator. The value written to this register is multiplied by
200 ns to get the threshold value. Therefore, if a value of 5 is
written, the digital comparator threshold is 1 μs and any pulses
less than 1 μs are rejected by the sync separator. There is some
variability to the 200 ns multiplier value. The maximum
variability over all operating conditions is ±20% (160 ns to 240 ns).
Since normal Vsync and Hsync pulse widths differ by a factor of
about 500 or more, the 20% variability is not an issue. The
power-up default value is 32 DDR.
0x12—Bit[7] Hsync Source Override
This is the active Hsync override. Setting this to 0 allows the
chip to determine the active Hsync source. Setting it to 1 uses
Bit 6 of Register 0x12 to determine the active Hsync source.
Power-up default value is 0.
Table 18. Active Hsync Source Override
Override
0
1
0x12—Bit[6] Hsync Source
This bit selects the source of the Hsync for PLL and sync
processing—only if Bit 7 of Register 0x12 is set to 1 or if both
syncs are active. Setting this bit to 0 specifies the Hsync from
the input pin. Setting it to 1 selects Hsync from SOG. Power-up
default is 0.
Table 19. Active Hsync Select Settings
Select
0
1
Result
Hsync input
Hsync from SOG
Result
Hsync source determined by chip
Hsync source determined by user
Register 0x12, Bit 6