ADF7021-VBCPZ-RL Analog Devices Inc, ADF7021-VBCPZ-RL Datasheet
ADF7021-VBCPZ-RL
Specifications of ADF7021-VBCPZ-RL
Related parts for ADF7021-VBCPZ-RL
ADF7021-VBCPZ-RL Summary of contents
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... Enhanced performance ADF7021-N with external VCO Frequency bands using external VCO: 80 MHz to 960 MHz Improved adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N Programmable IF filter bandwidths: 9 kHz, 13.5 kHz, and 18.5 kHz Modulation schemes: 2FSK, 3FSK, 4FSK, MSK Spectral shaping: Gaussian and raised cosine filtering Data rates: 0 ...
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... ADF7021-V TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 RF and PLL Specifications ........................................................... 4 Transmission Specifications ........................................................ 5 Receiver Specifications ................................................................ 6 Digital Specifications ................................................................... 9 General Specifications ............................................................... 10 Timing Characteristics .............................................................. 10 Timing Diagrams ........................................................................ 11 Absolute Maximum Ratings .......................................................... 14 ESD Caution ................................................................................ 14 Pin Configuration and Function Descriptions ........................... 15 Typical Performance Characteristics ........................................... 17 Frequency Synthesizer ...
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... The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz. The ADF7021-V supports a wide variety of pro- grammable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application ...
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... SPECIFICATIONS 3.6 V, GND = measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth. RF AND PLL SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Phase Frequency Detector (PFD) ...
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... Rev Page ADF7021-V Test Conditions/Comments Limited by the loop bandwidth LBW must be ≥1.25 × data rate for correct operation LBW = 18.5 kHz LBW = 18.5 kHz PFD = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz Programmable ...
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... RF 1 Measured as maximum unmodulated power. 2 Suitable for ETSI 500 mW Tx requirements. 3 Conductive filtered harmonic emissions measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor). RECEIVER SPECIFICATIONS LBW = loop bandwidth and IFBW = IF filter bandwidth. Table 3. Parameter Min DATA RATE 2FSK 0 ...
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... Desired signal above the sensitivity point of −109.5 dBm; rejection is measured as the level of an interferer to cause a BER of 10 −5 dB IFBW = 9 kHz, data rate = 4.8 kbps, f Rev Page ADF7021 1.2 kHz, high sensitivity mode, IFBW = 13 1.2 kHz, high sensitivity mode, IFBW = 13.5 kHz, = 860 MHz 100 kHz, ...
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... For received signal levels < −100 dBm recommended that the RSSI readback value be averaged over a number of samples to improve RSSI accuracy at low input power. 5 Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor). Typ ...
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... MHz V 0 Rev Page ADF7021-V Test Conditions/Comments CREG[1:4] = 100 nF 32-bit register write time = 50 μs Depends on VCO settling Depends on VCO settling 32-bit register write time = 50 μs, IF filter coarse calibration only Depends on VCO settling Depends on VCO settling Time to synchronized data output; includes AGC settling (three AGC levels) and CDR synchronization ...
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... POWER-DOWN CURRENT CONSUMPTION Low Power Sleep Mode 1 The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards. Improved PA efficiency is achieved by using a separate PA matching network. 2 Device current only. VCO and TCXO currents are excluded. ...
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... Figure 2. Serial Interface Timing Diagram X RV16 RV15 t 9 Figure 3. Serial Interface Readback Timing Diagram 1/DATA RATE DATA Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode 1/DATA RATE DATA SAMPLE Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode Rev Page ADF7021-V DB1 DB0 (LSB) (CONTROL BIT C1 RV2 RV1 X ...
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... ADF7021-V 4FSK Timing In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by detection of the SWD pin in the receive bit stream. t SYMBOL t BIT SLE TxRxCLK Rx SYMBOL TxRxDATA MSB Tx/Rx MODE SLE TxRxCLK Tx SYMBOL TxRxDATA MSB Tx/Rx MODE REGISTER 0 WRITE SYMBOL Rx SYMBOL Rx SYMBOL LSB LSB ...
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... DATA OUTPUT IN UART/SPI MODE.) Tx/Rx MODE FETCH SAMPLE Tx BIT Tx BIT Tx BIT Tx BIT HIGH-Z Tx MODE Figure 8. Transmit Timing Diagram in UART/SPI Mode t FETCH SAMPLE HIGH-Z Rx BIT Rx BIT Rx BIT Rx BIT Rx MODE Figure 9. Receive Timing Diagram in UART/SPI Mode Rev Page ADF7021-V t BIT Tx BIT BIT Rx BIT ...
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... ADF7021-V ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 7. Parameter Rating GND −0 Analog I/O Voltage to GND −0 VDDx + 0 Digital I/O Voltage to GND −0 VDDx + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150° ...
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... Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected Chip Enable. Bringing CE low puts the ADF7021-V into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed after CE is brought high. 25 SLE Load Enable, CMOS Input ...
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... Voltage Supply for Digital Block. Place a decoupling capacitor close as possible to this pin. Tie all VDDx pins together. 33 SWD Sync Word Detect. The ADF7021-V asserts this pin when it finds a match for the sync word sequence. This provides an interrupt for an external microcontroller, indicating that valid data is being received. 34 TxRxDATA Transmit Data Input/Received Data Output ...
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... FREQUENCY (MHz) 10 DATA RATE = 9.6kbps DATA = PRBS9 2.4kHz DEV RF FREQ = 868MHz 2FSK GFSK 867.97 867.98 867.99 868.00 868.01 FREQUENCY (MHz) Figure 16. Output Spectrum in 2FSK and GFSK Modes ADF7021-V 2800 868.02 868.03 ...
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... ADF7021 –10 –20 –30 –40 –50 RC2FSK –60 –70 –80 867.97 867.98 867.99 868.00 868.01 FREQUENCY (MHz) Figure 17. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes 10 DATA RATE = 9.6kbps DATA = PRBS9 FREQ = 868MHz –10 –20 –30 –40 –50 –60 RC3FSK –70 – ...
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... Figure 27. Image Rejection, Uncalibrated vs. Calibrated 2.5 0 +90°C –2.5 –5.0 –7.5 –10.0 –12.5 –15.0 –17.5 –40°C –20.0 –22.5 –25.0 –27.5 –30.0 –32.5 –35.0 –37 100 102 104 IF FREQUENCY (kHz) Figure 28. Variation of IF Filter Response with Temperature ADF7021-V RSSI –52.5 –42.5 106 108 110 ...
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... ADF7021-V –100 –102 –104 –106 –108 DISCRIMINATOR BANDWIDTH = –110 2× FSK FREQUENCY DEVIATION –112 –114 –116 DISCRIMINATOR BANDWIDTH = 1× FSK FREQUENCY DEVIATION –118 0 0.2 0.4 0.6 MODULATION INDEX Figure 29. 2FSK Sensitivity vs. Modulation Index and Correlator Discriminator Bandwidth 0 –1 THRESHOLD DETECTION –2 VITERBI DETECTION – ...
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... Using a TCXO Reference A single-ended reference (TCXO, VCXO, or OCXO) can also be used with the ADF7021-V. This is recommended for applications that have absolute frequency accuracy requirements of <10 ppm, such as applications requiring compliance with ARIB STD-T67 or ETSI EN 300 220. The following are two options for inter- facing the ADF7021 external reference oscillator. • ...
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... ADF7021-V The free design tool ADIsimSRD™ Design Studio can also be used to design loop filters for the ADF7021-V. See the ADIsimSRD Design Studio website (www.analog.com/adisimsrd) for details). N Counter The feedback divider in the ADF7021-V PLL consists of an 8-bit integer counter (set using Register 0, Bits[DB26:DB19]) and a 15-bit, Σ ...
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... ACP, as well as improved ACR, blocking, and image rejection in the receiver. The maximum VCO frequency of operation supported on the ADF7021-V is 1920 MHz, which results in a maximum RF channel frequency of 960 MHz using a 2× VCO or 480 MHz using a 4× VCO. EXTERNAL ...
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... ADF7021-V TRANSMITTER RF OUTPUT STAGE The power amplifier (PA) of the ADF7021-V is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum frequency of 960 MHz. The PA output current and, consequently, the output power are programmable over a wide range. The PA configuration is shown in Figure 38 ...
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... C DEV C C DEV RF FREQUENCY Figure 41. 3FSK Symbol-to-Frequency Mapping 2 P( − CONVOLUTIONAL PRECODER ENCODER 1/P(D) P(D) 0, +1, – FSK MOD C f CONTROL C AND DATA FILTERING Figure 42. 3FSK Encoding ADF7021-V − DEV + DEV + f C DEV shaping filter DEV f – DEV TO N DIVIDER ...
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... The transmit clock from Pin TxRxCLK is available after writing to Register 3 in the power-up sequence for receive mode. The MSB of the first symbol should be clocked into the ADF7021-V on the first transmit clock pulse from the ADF7021-V after writing to Register 3. See Figure 6 and Figure 7 for more timing ...
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... RF output. The latency without any data filtering is 1 bit. The addition of data filtering adds a further latency as indicated in Table 11 important that the ADF7021-V be left in transmit mode after the last data bit is sampled by the data clock to account for this latency. The ADF7021-V should stay in transmit mode for a time equal to the number of latency bit periods for the applied modulation scheme ...
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... ADF7021-V RECEIVER SECTION RF FRONT END The ADF7021-V is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerline-induced interference problems. Figure 44 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption to best suit their application ...
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... Rev Page Filter Gain Gain Mode (FG2, FG1) Correction Sensitivity (2FSK, Rx Current Data Rate = 4.8 kbps kHz) (dBm) Consumption (mA) DEV −116.5 20.1 −113 20.1 −108 17.9 −102 17.9 −99 17.9 −91 17.9 ADF7021-V Input IP3 (dBm) −24 −20 −13.5 −9 −5 −3 ...
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... ADF7021-V DEMODULATION, DETECTION, AND CDR System Overview An overview of the demodulation, detection, and clock and data recovery (CDR) of the received signal on the ADF7021-V is shown in Figure 46. LIMITERS I CORRELATOR Q DEMODULATOR MUX LINEAR DEMODULATOR TxRxDATA 2FSK/3FSK/4FSK CLOCK AND MUX DATA TxRxCLK RECOVERY Figure 46. Overview of Demodulation, Detection, and CDR Process ...
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... In 3FSK modulation, the linear convolutional encoder scheme guarantees that the transmitted symbol sequence is dc-free, facilitating symbol detection. However, Tx data scrambling is recommended to limit the run length of 0 symbols in the transmit bit stream. Using 3FSK, the CDR data rate tolerance is typically ±0.5%. Rev Page ADF7021-V ...
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... ADF7021-V RECEIVER SETUP Correlator Demodulator Setup To enable the correlator for various modulation modes, see Table 15. Table 15. Enabling the Correlator Demodulator DEMOD_SCHEME Received Modulation (Register 4, Bits[DB6:DB4]) 2FSK 001 3FSK 010 4FSK 011 To optimize receiver sensitivity, the correlator bandwidth must be optimized for the specific deviation frequency and modula- tion used by the transmitter ...
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... CDR acquisition (see Table 20). The remaining fields that follow the preamble do not need to use dc-free coding. For these fields, the ADF7021-V can accom- modate coding schemes with a run length of greater than eight bits without any performance degradation. Refer to the AN-915 Application Note for more information ...
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... AFC OPERATION The ADF7021-V also supports a real-time AFC loop that is used to remove frequency errors due to mismatches between the transmit and receive crystals/TCXOs. The AFC loop uses the linear frequency discriminator block to estimate frequency errors ...
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... ADF7021-V. In receive mode, this preprogrammed word is compared to the received bit stream. When a valid match is identified, the external SWD pin is asserted by the ADF7021-V on the next Rx clock pulse. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption ...
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... When initiated by writing to the part, calibration is performed automatically without user intervention. The calibration time is 200 μs for coarse calibration and 8.2 ms for fine calibration, during which time the ADF7021-V should not be accessed. The IF filter calibration logic requires that the IF_FILTER_DIVIDER bits (Register 5, Bits[DB13:DB5]) be set such that ...
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... IF Filter Variation with Temperature When calibrated, the filter center frequency can vary with changes in temperature. If the ADF7021-V is used in an application where it remains in receive mode for a considerable length of time, the user must consider this variation of filter center frequency with temperature. This variation is typically 1 kHz per 20° ...
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... Table 14. IMAGE REJECTION CALIBRATION The image channel in the ADF7021-V is 200 kHz below the desired signal. The polyphase filter rejects this image with an asymmetric frequency response. The image rejection (IR) performance of the receiver is dependent on how well matched the I and Q signals are in amplitude and how well matched the quadrature is between them (that is, how close to 90° ...
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... PROGRAMMING AFTER INITIAL POWER-UP CAL AT –40°C Table 23 lists the minimum number of writes needed to set up the ADF7021-V in either mode after CE is brought high for a minimum of 100 μs before programming any register. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC ...
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... ADF7021-V The recommended programming sequences for transmit and receive are shown in Figure 54 and Figure 55, respectively. REFERENCE CE HIGH WAIT 50µs (REGULATOR POWER-UP) CHECK FOR REGULATOR READY OPTIONAL. ONLY NECESSARY IF PA RAMP-DOWN IS REQUIRED. The difference in the power-up routine for a TCXO and XTAL reference is shown in these figures. ...
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... CE LOW REFERENCE WAIT 50µs + 1ms (REGULATOR POWER-UP + TYPICAL XTAL SETTLING) CHECK FOR REGULATOR READY WRITE TO REGISTER 1 (TURNS ON Tx/Rx CLOCKS) Rx MODE CE LOW POWER-DOWN Rev Page ADF7021-V CE HIGH OPTIONAL: ONLY NECESSARY IF IF FILTER FINE CALIBRATION IS REQUIRED. OPTIONAL: ONLY NECESSARY IF SWD IS REQUIRED. OPTIONAL: ONLY NECESSARY IF ...
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... Figure 56. Typical Application Circuit (Regulator Capacitors and Power Supply Decoupling Not Shown) For recommended component values, see the ADF7021-V evaluation board data sheet and the AN-859 Application Note, accessible from the ADF7021-V product page. Follow the refer- ence design schematic closely to ensure optimum performance in narrow-band applications. ...
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... RV8 RV7 RV6 RV5 RV4 RV3 RV2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 X RV7 RV6 RV5 RV4 RV3 RV2 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV8 RV7 RV6 RV5 RV4 RV3 RV2 ADF7021-V DB0 RV1 RV1 RV1 RV1 RV1 ...
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... Bit RV16 to Bit RV5. The revision code (RC) is coded with one quartet extending from Bit RV4 to Bit RV1. The product code for the ADF7021-V should read back 0x212. The current revision code should read 0x0. Filter Bandwidth Calibration Readback The filter calibration readback word is contained in Bit RV8 to Bit RV1 (see Figure 57) ...
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... DIGITAL_LOCK_DETECT indicates when the PLL has locked. RSSI_READY indicates that the RSSI signal has settled and an RSSI readback can be performed. Tx_Rx gives the status of Bit DB27 in this register, which can be used to control an external Tx/Rx switch. ADF7021-V ADDRESS BITS FRACTIONAL_N DIVIDE RATIO 0 ...
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... ADF7021-V REGISTER 1—OSCILLATOR REGISTER RESERVED RFD1 RF_DIVIDE_BY_2 0 1 VE1 0 1 • The R_COUNTER and XTAL_DOUBLER relationship is as follows: If XTAL_DOUBLER = 0, XTAL = PFD R _ COUNTER If XTAL_DOUBLER = 1, × XTAL 2 = PFD R _ COUNTER XTAL_ CLKOUT_ BIAS OFF ON BUFFER_ IMPEDANCE 50Ω HIGH IMPEDANCE XTAL_ D1 DOUBLER 0 DISABLED ...
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... R-COSINE_ALPHA sets the roll-off factor (alpha) of the raised cosine data filter to either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by × using an alpha of 0.7. ON PFD Rev Page ADF7021-V MODULATION_ ADDRESS SCHEME PA_RAMP BITS PE1 PA_ENABLE 0 ...
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... ADF7021-V REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER AGC_CLK_DIVIDE SEQ_CLK_DIVIDE GD6 GD5 GD4 GD3 GD2 GD1 ... ... ... ... ... ... • Baseband offset clock frequency (BBOS CLK) must be greater than 1 MHz and less than 2 MHz, where BBOS CLK = (XTAL/BBOS_CLK_DIVIDE) • Set the demodulator clock (DEMOD CLK) such that 2 MHz ≤ ...
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... DEMOD CLK where f (the cutoff frequency of the postdemodulator CUTOFF filter) should typically be set equal to 0.75 × the data rate in 2FSK. In 3FSK, it should be set equal to the data rate, whereas in 4FSK, it should be set equal to 1.6 × the symbol rate. ADF7021-V ADDRESS BITS ...
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... ADF7021-V REGISTER 5—IF FILTER SETUP REGISTER IR_GAIN_ ADJUST_MAG PM4 PD1 IR_PHASE_ADJUST_DIRECTION 0 ADJUST ADJUST Q CH GM5 GM4 GM3 GM2 GM1 GQ1 IR_GAIN_ADJUST_I/Q 0 ADJUST ADJUST Q CH GA1 IR_GAIN_ADJUST_UP/DN 0 GAIN 1 ATTENUATE • A coarse IF filter calibration is performed when the IF_CAL_COARSE bit (Bit DB4) is set. If the IF_FINE_ ...
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... LEVEL bits (Bits[DB29:DB28]) set the drive strength of the source, whereas the IR_CAL_SOURCE ÷2 bit (Bit DB30) allows the frequency of the internal signal source to be divided by 2. Upper Tone Frequency (kHz) 116.3 116.3 119 Rev Page ADF7021-V IF_CAL_LOWER_TONE_DIVIDE FC1 IF_FINE_CAL 0 DISABLED 1 ENABLED IF_CAL_LOWER_ LT3 ...
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... ADF7021-V REGISTER 7—READBACK SETUP REGISTER RB3 READBACK_SELECT 0 DISABLED 1 ENABLED • Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, temperature sensor, or voltage at the external ADCIN pin is not valid in Rx mode. • To read back the battery voltage, the temperature sensor, or ...
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... DEMOD OFF 1 DEMOD ON Figure 70. Register 8—Power-Down Test Register Map For a combined LNA/PA matching network, Bit DB11 should always be set to 0, which enables the internal Tx/Rx switch. This is the power-up default condition. Rev Page ADF7021-V CONTROL BITS DB6 DB5 DB4 DB3 DB2 ...
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... ADF7021-V REGISTER 9—AGC REGISTER LNA_ BIAS ML1 MIXER_LINEARITY 0 DEFAULT 1 HIGH LI2 LI1 LNA_BIAS 0 0 800µA (DEFAULT) LM1 LNA_MODE 0 DEFAULT 1 REDUCED GAIN FI1 FILTER_CURRENT 0 LOW 1 HIGH FG2 FG1 FILTER_GAIN INVALID • necessary to program this register only if AGC settings other than the defaults are required. ...
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... Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the AFC. Rev Page ADDRESS BITS AE1 AFC_EN 0 AFC OFF 1 AFC ON AFC_SCALING_ ... FACTOR ... ... ... ... ... . . . . ... . . . . ... . . . . ... 4093 ... 4094 ... 4095 ADF7021-V ...
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... ADF7021-V REGISTER 11—SYNC WORD DETECT REGISTER REGISTER 12—SWD/THRESHOLD SETUP REGISTER ILx SWD_MODE Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation SYNC_BYTE_SEQUENCE Figure 73. Register 11—Sync Word Detect Register Map DATA_PACKET_LENGTH DPx DATA_PACKET_LENGTH 0 INVALID ...
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... OFF PHASE_ 2 PC1 CORRECTION DISABLED . . . 1 ENABLED 1 1 127 ST7 VITERBI_PATH _ 0 MEMORY VM2 VM1 BITS BITS . BITS BITS . 1 3FSK_PREMABLE_ TIME_VALIDATE Figure 75. Register 13—3FSK/4FSK Demodulation Register Map Rev Page 3FSK/4FSK_ CONTROL SLICER_THRESHOLD BITS 3FSK/4FSK_SLICER_ ST3 ST2 ST1 ... THRESHOLD ... OFF ... 1 ... ... ... . . . . . . . ... . ... 127 ADF7021-V ...
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... ADF7021-V REGISTER 14—TEST DAC REGISTER TEST_DAC_GAIN EFx ED_LEAK_FACTOR ERx PULSE_EXTENSION LEAKAGE = 0 0 2^– 2^– 2^– 2^–11 4 2^–12 5 2^–13 6 2^–14 7 2^–15 PEx ED_PEAK_RESPONSE 0 FULL RESPONSE TO PEAK 1 0.5 RESPONSE TO PEAK 2 0.25 RESPONSE TO PEAK 3 0.125 RESPONSE TO PEAK The demodulator tuning parameters, PULSE_EXTENSION, ED_LEAK_FACTOR, and ED_PEAK_RESPONSE, can be enabled only by setting Register 15, Bits[DB7:DB4] to 0x9 ...
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... BB OFFSET CLK Σ-Δ CLK 5 6 ADC CLK 7 TxRxCLK Figure 77. Register 15—Test Mode Register Map • The CDR block can be bypassed by setting Rx_TEST_ MODES depending on the demodulator used. Rev Page ADF7021-V Tx_TEST_ Rx_TEST_ ADDRESS MODES MODES BITS f TONE ONLY DEV f TONE ONLY ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADF7021-VBCPZ −40°C to +85°C ADF7021-VBCPZ-RL −40°C to +85°C EVAL-ADF70XXMBZ2 EVAL-ADF7021-VDB1Z EVAL-ADF7021-VDB2Z RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...