ADF7021-VBCPZ-RL Analog Devices Inc, ADF7021-VBCPZ-RL Datasheet - Page 28

• Manufacturer Part Number: ADF7021-VBCPZ-RL
• Description: Narrow Band Transceiver 433/868/900 MHz
• Manufacturer: Analog Devices Inc

Specifications of ADF7021-VBCPZ-RL

• Frequency: 80MHz ~ 960MHz
• Data Rate - Maximum: 24 kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 13dBm
• Sensitivity: -125dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 21.7mA
• Current - Transmitting: 27.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7021-V
RECEIVER SECTION
RF FRONT END
The ADF7021-V is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low external
component count and does not suffer from powerline-induced
interference problems.
Figure 44 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption to best suit their application.
To achieve a high level of resilience against spurious reception,
the low noise amplifier (LNA) features a differential input.
Switch SW2 shorts the LNA input when transmit mode is
selected (Register 0, Bit DB27 = 0). This feature facilitates the
design of a combined LNA/PA matching network, avoiding the
need for an external Tx/Rx switch. See the LNA/PA Matching
section for details on the design of the matching network.
The LNA is followed by a quadrature downconversion mixer,
which converts the RF signal to the IF frequency of 100 kHz.
An important consideration is that the output frequency of the
synthesizer must be programmed to a value 100 kHz below the
center frequency of the received channel. The LNA has two
basic operating modes: high gain/low noise mode and low gain/
low power mode. To switch between these two modes, use the
LNA_MODE bit (Register 9, Bit DB25). The mixer is also config-
urable for either a low current mode or an enhanced linearity
mode using the MIXER_LINEARITY bit (Register 9, Bit DB28).
Based on the specific sensitivity and linearity requirements of
the application, it is recommended that the LNA_MODE bit and
the MIXER_LINEARITY bit be adjusted as shown in Table 14.
The gain of the LNA is configured by the LNA_GAIN bits
(Register 9, Bits[DB21:DB20]) and can be set by the user or by
the automatic gain control (AGC) logic.
IF FILTER
IF Filter Settings
Out-of-band interference is rejected by means of a fifth-order
Butterworth polyphase IF filter centered on a frequency of
100 kHz. The bandwidth of the IF filter can be programmed to
9 kHz, 13.5 kHz, or 18.5 kHz in Register 4, Bits[DB31:DB30],
and should be chosen as a compromise between interference
rejection and attenuation of the desired signal.
(REG 0, BIT DB27)
(REG 9, BITS[DB27:DB26])
(REG 9, BITS[DB21:DB20])
Tx/Rx SELECT
LNA/MIXER_ENABLE
(REG 9, BIT DB25)
(REG 8, BIT DB6)
LNA_MODE
LNA_GAIN
RFIN
RFIN
LNA_BIAS
Figure 44. RF Front End
SW2
LNA
MIXER_LINEARITY
(REG 9, BIT DB28)
LO
I (TO FILTER)
Q (TO FILTER)
Rev. 0 | Page 28 of 60
If the AGC loop is disabled, the gain of the IF filter can be set to
one of three levels by using the FILTER_GAIN bits (Register 9,
Bits[DB23:DB22]). The filter gain is adjusted automatically if
the AGC loop is enabled.
IF Filter Bandwidth and Center Frequency Calibration
To compensate for manufacturing tolerances, the IF filter should
be calibrated after power-up to ensure that the bandwidth and
center frequency are correct. Coarse and fine calibration schemes
are provided to offer a choice between fast calibration (coarse
calibration) and high filter centering accuracy (fine calibration).
Coarse calibration is enabled by setting Register 5, Bit DB4 high.
Fine calibration is enabled by setting Register 6, Bit DB4 high.
For details on when it is necessary to perform a filter calibration,
and in what applications to use either a coarse calibration or
fine calibration, see the IF Filter Bandwidth Calibration section.
RSSI/AGC
The RSSI is implemented as a successive compression log amp
following the baseband (BB) channel filtering. The log amp
achieves ±3 dB log linearity. It also doubles as a limiter to
convert the signal-to-digital levels for the FSK demodulator.
The offset correction circuit uses the BBOS_CLK_DIVIDE bits
(Bits DB5:DB4] in Register 3) and should be set between 1 MHz
and 2 MHz. The RSSI level is converted for user readback and
for digitally controlled AGC by an 80-level (7-bit) flash ADC.
This level can be converted to input power in dBm. By default,
the AGC is on when powered up in receive mode.
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD (Register 9,
Bits[DB17:DB11]), the gain is reduced. When the RSSI is below
AGC_LOW_THRESHOLD (Register 9, Bits[DB10:DB4]), the
gain is increased. The thresholds default to 70 (high threshold)
and 30 (low threshold) on power-up in receive mode. A delay
(set by AGC_CLK_DIVIDE in Register 3, Bits[DB31:DB26]) is
programmed to allow for settling of the loop. A value of 33 is
recommended to give an AGC update rate of 3 kHz.
The user has the option of changing the two threshold values
from the defaults of 70 and 30 (Register 9). The default AGC
setup values should be adequate for most applications. The
threshold values must be more than 30 apart for the AGC to
operate correctly.
1
IFWR
CORRECTION
A
OFFSET
IFWR
Figure 45. RSSI Block Diagram
A
R
IFWR
A
IFWR
LATCH
CLK
FSK
DEMOD
ADC
RSSI