ADF7021-VBCPZ-RL Analog Devices Inc, ADF7021-VBCPZ-RL Datasheet - Page 10

• Manufacturer Part Number: ADF7021-VBCPZ-RL
• Description: Narrow Band Transceiver 433/868/900 MHz
• Manufacturer: Analog Devices Inc

Specifications of ADF7021-VBCPZ-RL

• Frequency: 80MHz ~ 960MHz
• Data Rate - Maximum: 24 kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 13dBm
• Sensitivity: -125dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 21.7mA
• Current - Transmitting: 27.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7021-V
GENERAL SPECIFICATIONS
Table 5.
Parameter
TEMPERATURE RANGE (T
POWER SUPPLIES
TRANSMIT CURRENT CONSUMPTION
RECEIVE CURRENT CONSUMPTION
POWER-DOWN CURRENT CONSUMPTION
1
2
TIMING CHARACTERISTICS
V
Table 6.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
8
9
10
11
12
13
14
15
The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards.
Improved PA efficiency is achieved by using a separate PA matching network.
Device current only. VCO and TCXO currents are excluded.
DD
Voltage Supply, V
868 MHz
460 MHz
868 MHz
460 MHz
Low Power Sleep Mode
= 3 V ± 10%, GND = 0 V, T
0 dBm
5 dBm
10 dBm
0 dBm
5 dBm
10 dBm
Low Current Mode
High Sensitivity Mode
Low Current Mode
High Sensitivity Mode
DD
Limit at T
>10
>10
>25
>25
>10
>20
<25
<25
>10
5 < t
>5
>5
5 < t
>¼ × t
A
)
11
14
< (¼ × t
< (¼ × t
BIT
MIN
A
= 25°C, unless otherwise noted. Guaranteed by design but not production tested.
2
to T
BIT
BIT
1, 2
)
)
MAX
2
Min
−40
2.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
Rev. 0 | Page 10 of 60
Typ
17.6
20.8
27.1
13.8
17
23
19.3
21.7
16.3
18.3
0.1
Description
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
SLE pulse width
SCLK to SREAD data valid, readback
SREAD hold time after SCLK, readback
SCLK to SLE disable time, readback
TxRxCLK negative edge to SLE
TxRxDATA to TxRxCLK setup time (Tx mode)
TxRxCLK to TxRxDATA hold time (Tx mode)
TxRxCLK negative edge to SLE
SLE positive edge to positive edge of TxRxCLK (Rx mode)
Max
+85
3.6
1
Unit
°C
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
Test Conditions/Comments
All VDDx pins must be tied together
V
V
CE low
DD
DD
= 3.0 V, PA is matched into 50 Ω
= 3.0 V