ADF7025BCPZ-RL7 Analog Devices Inc, ADF7025BCPZ-RL7 Datasheet - Page 5

• Manufacturer Part Number: ADF7025BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7025BCPZ-RL7

• Frequency: 431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
• Data Rate - Maximum: 384kbps
• Modulation Or Protocol: FSK
• Applications: Keyless Entery, Home Automation, Wireless Audio/Video
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -104dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Parameter
CHANNEL FILTERING
BLOCKING
PHASE-LOCKED LOOP
REFERENCE INPUT
TIMING INFORMATION
Adjacent Channel Rejection
Second Adjacent Channel Rejection
Third Adjacent Channel Rejection
Co-Channel Rejection
Wideband Interference Rejection
±1 MHz
±2 MHz
±10 MHz
Saturation (Maximum Input Level)
LNA Input Impedance
RSSI
VCO Gain
Phase Noise (In-Band)
Phase Noise (Out-of-Band)
Residual FM
PLL Settling Time
Crystal Reference
External Oscillator
Load Capacitance
Crystal Start-Up Time
Input Level
Chip Enabled to Regulator Ready
Crystal Oscillator Startup Time
Tx to Rx Turnaround Time
(Offset = ±1 × LP Filter BW Setting)
(Offset = ±2 × LP Filter BW Setting)
(Offset = ±3 × LP Filter BW Setting)
Range at Input
Linearity
Absolute Accuracy
Response Time
Min
3.625
3.625
Typ
27
40
43
−2
42
51
64
12
24 − j60
26 − j63
71 − j128
−100 to
−36
±2
±3
65
83
−89
−110
128
40
33
1
150 µs +
(5 × T
70
150
1.0
10
Rev. A | Page 5 of 44
BIT
)
Max
+24
24
24
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dBm
Ω
Ω
Ω
dBm
dB
dB
µs
MHz/V
MHz/V
dBc/Hz
dBc/Hz
Hz
µs
MHz
MHz
pF
ms
CMOS
µs
ms
levels
Desired signal (38.4 kbps DR, 200 kHz FDEV,
Test Conditions
Desired signal (38.4 kbps DR, 200 kHz FDEV,
Maximum rejection measured with CW
Swept from 100 MHz to 2 GHz,
FSK mode, BER = 10
FRF = 915 MHz, RFIN to GND
FRF = 868 MHz
FRF = 433 MHz
902 MHz to 928 MHz band,
862 MHz to 870 MHz band,
PA = 0 dBm, V
1 MHz offset
From 200 Hz to 20 kHz, FRF = 868MHz
Measured for a 10 MHz frequency step
Using 33 pF load capacitors
C
With 19.2 MHz XTAL
Time to synchronized data,
REG
VCO adjust = 3, VCO_BIAS_SETTING = 12
VCO adjust = 0, VCO_BIAS_SETTING = 10
±300 KHz LP filter B/W) 6 dB above the
input sensitivity level, CW interferer power
level increased until BER = 10
interferer at center of channel
measured as channel rejection
±300 KHz LP filter B/W) 6 dB above the
input sensitivity level, CW interferer power
level increased until BER = 10
FRF = 868 MHz, VCO_BIAS_SETTING = 10
to within 5 ppm accuracy,
PFD = 20 MHz, LBW = 50kHz
includes AGC settling
= 100 nF
DD
= 3.0 V, PFD = 10 MHz,
−3
ADF7025
−3
−3