ADSP-21261SKBCZ150 Analog Devices Inc, ADSP-21261SKBCZ150 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21261SKBCZ150
• Description: 150 MHz, 32Bit DSP Processor
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKBCZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21261/ADSP-21262/ADSP-21266
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SCLK)
(SCLK)
(FS)
(FS)
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
t
t
t
DRIVE EDGE
DRIVE EDGE
HOFSI
HDTI
HOFSI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DATA RECEIVE—INTERNAL CLOCK
SCLK (INT)
SCLK (EXT)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
t
DFSI
t
DFSI
t
t
SCLKIW
SCLKIW
t
DDTI
DRIVE EDGE
DRIVE EDGE
t
t
t
SDRI
SFSI
SFSI
SAMPLE EDGE
SAMPLE EDGE
Rev. F | Page 30 of 44 | July 2009
t
DDTIN
t
Figure 21. Serial Ports
DDTEN
t
t
t
HFSI
HFSI
HDRI
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SCLK)
(SCLK)
(FS)
(FS)
t
t
DRIVE EDGE
DRIVE EDGE
HOFSE
HDTE
t
HOFSE
SCLK
DATA TRANSMIT—EXTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
t
t
DFSE
DFSE
t
DDTTE
t
SCLKW
t
SCLKW
DRIVE EDGE
t
DDTE
t
t
SFSE
t
SDRE
SFSE
SAMPLE EDGE
SAMPLE EDGE
t
t
HFSE
t
HFSE
HDRE