ADSP-21261SKBCZ150 Analog Devices Inc, ADSP-21261SKBCZ150 Datasheet - Page 31

• Manufacturer Part Number: ADSP-21261SKBCZ150
• Description: 150 MHz, 32Bit DSP Processor
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKBCZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Data Port (IDP)
The timing requirements for the IDP are given in
Figure
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 33. Input Data Port (IDP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
CLKIN or any of the DAI pins.
22. IDP Signals (SCLK, FS, SDATA) are routed to the
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20
DAI_P20
DAI_P20
(SDATA)
(SCLK)
(FS)
–
–
–
1
1
1
1
Table 33
1
1
Rev. F | Page 31 of 44 | July 2009
Figure 22. Input Data Port (IDP)
1
and
t
IDPCLKW
t
SISFS
t
SISD
ADSP-21261/ADSP-21262/ADSP-21266
SAMPLE EDGE
Min
2.5
2.5
2.5
2.5
7
20
t
t
SIHFS
SIHD
Max
Unit
ns
ns
ns
ns
ns
ns