ADSP-2191MKCAZ-160 Analog Devices Inc, ADSP-2191MKCAZ-160 Datasheet - Page 16

• Manufacturer Part Number: ADSP-2191MKCAZ-160
• Description: 16-bit,160 MIPS, 2.5V,160K Bytes RAM
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2191MKCAZ-160

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-MBGA, 144-Mini-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-2191M
Table 7. Pin Function Descriptions (continued)
Pin
PF5
PF4
PF3
PF2
PF1
PF0
RD
WR
ACK
BMS
IOMS
MS3–0
BR
BG
BGH
HAD15–0
HA16
HACK_P
HRD
HWR
HACK
HALE
HCMS
HCIOMS
CLKIN
XTAL
BMODE1–0
OPMODE
CLKOUT
BYPASS
RCLK1–0
RCLK2/SCK1
RFS1–0
RFS2/MOSI1
TCLK1–0
TCLK2/SCK0
TFS1–0
TFS2/MOSI0
DR1–0
DR2/MISO1
DT1–0
DT2/MISO0
/SPI1SEL2
/MSEL5
/SPI0SEL2
/MSEL4
/SPI1SEL1
/MSEL3
/SPI0SEL1
/MSEL2
/SPISS1
/MSEL1
/SPISS0
/MSEL0
Type
I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
I/O/T
I
I
O/T
O/T
I
O/T
O/T
O/T
I
O
O
I/O/T
I
I
I
I
O
I
I
I
I
O
I
I
O
I
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/T
I/O/T
O/T
I/O/T
Function
Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5
(during boot)
Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4
(during boot)
Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3
(during boot)
Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2
(during boot)
Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1
(during boot)
Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0
(during boot)
External Port Read Strobe
External Port Write Strobe
External Port Access Ready Acknowledge
External Port Boot Space Select
External Port IO Space Select
External Port Memory Space Selects
External Port Bus Request
External Port Bus Grant
External Port Bus Grant Hang
Host Port Multiplexed Address and Data Bus
Host Port MSB of Address Bus
Host Port ACK Polarity
Host Port Read Strobe
Host Port Write Strobe
Host Port Access Ready Acknowledge
Host Port Address Latch Strobe or Address Cycle Control
Host Port Internal Memory–Internal I/O Memory–Boot Memory Select
Host Port Internal I/O Memory Select
Clock Input/Oscillator Input
Oscillator Output
Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85 kΩ internal pull-up resistors.
Operating Mode. The OPMODE pin has a 85 kΩ internal pull-up resistor.
Clock Output
Phase-Lock-Loop (PLL) Bypass Mode. The BYPASS pin has a 85 kΩ internal pull-up resistor.
SPORT1–0 Receive Clock
SPORT2 Receive Clock/SPI1 Serial Clock
SPORT1–0 Receive Frame Sync
SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input Data
SPORT1–0 Transmit Clock
SPORT2 Transmit Clock/SPI0 Serial Clock
SPORT1–0 Transmit Frame Sync
SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input Data
SPORT1–0 Serial Data Receive
SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output Data
SPORT1–0 Serial Data Transmit
SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output Data
–16–
REV. A