ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 2

• Manufacturer Part Number: ADSP-BF514BBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514BBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package: 168CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
Revision History ...................................................... 2
General Description ................................................. 3
REVISION HISTORY
1/11—Rev. A to Rev. B
This data sheet release coincides with the release of the revised
ADSP-BF51x Blackfin Processor Hardware Reference. All
redundant information has been removed.
Revised several specifications in
Revised f
Conditions ........................................................... 21
Revised several specifications in
Added additional f
Clock and Reset Timing .......................................... 27
Changed the parameter V
Memory Read Cycle Timing ..................................... 29
SDRAM Interface Timing ........................................ 31
Parallel Peripheral Interface Timing ........................... 33
Serial Ports ........................................................... 37
Revised t
ing ..................................................................... 33
Revised t
Parallel Peripheral Interface Timing ........................... 33
Revised the t
RSI Controller Timing ............................................ 35
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 5
Event Handling .................................................... 6
DMA Controllers .................................................. 7
Processor Peripherals ............................................. 7
Dynamic Power Management ................................ 11
Voltage Regulation Interface .................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 15
Development Tools ............................................. 15
Designing an Emulator-Compatible
Related Documents ............................................. 16
Processor Board (Target) ................................... 16
VCO
HFSPE
HFSPE
WL
specification in
specification in
specification and added the t
and t
CKIN
WH
specification for automotive models in
specifications in
DDMEM
Phase-Locked Loop Operating
Parallel Peripheral Interface Tim-
Operating Conditions ... 20
Electrical Characteristics 22
to V
DDEXT
in
PSUD
Asynchronous
specification in
Rev. B | Page 2 of 68 | January 2011
Signal Descriptions ................................................. 17
Specifications ........................................................ 20
176-Lead LQFP Lead Assignment ............................... 57
168-Ball CSP_BGA Ball Assignment ........................... 60
Outline Dimensions ................................................ 63
Automotive Products .............................................. 65
Ordering Guide ..................................................... 65
Revised t
(High Speed Mode) ................................................. 36
Revised t
MAC Controller Timing: MII Station Management ........ 48
Corrected dimensions in
Array [CSP_BGA] (BC-168-1) ................................... 64
Related Signal Chains ........................................... 16
Lockbox Secure Technology Disclaimer .................... 16
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 22
Flash Memory Characteristics ................................ 24
Absolute Maximum Ratings ................................... 25
Package Information ............................................ 26
ESD Sensitivity ................................................... 26
Timing Specifications ........................................... 27
Output Drive Currents ......................................... 50
Test Conditions .................................................. 52
Thermal Characteristics ........................................ 56
Surface-Mount Design .......................................... 64
WL
MDCIH
, t
WH
and t
and t
MDCOH
OH
specification in
168-Ball Chip Scale Package Ball Grid
specifications in
RSI Controller Timing
10/100 Ethernet