ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 46
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ADSP-BF514BBCZ-4F4
Manufacturer Part Number
ADSP-BF514BBCZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514BBCZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514BBCZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
168-LFBGA
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Package
168CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
400 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
AD
Quantity:
204
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 44. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
1
Table 45. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
1
Parameter
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
MII outputs synchronous to ETxCLK are ETxD3–0.
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
ETF
ETXCLKW
ETXCLKOV
ETXCLKOH
EREFCLKF
EREFCLKW
EREFCLKIS
EREFCLKIH
1
1
REF_CLK Frequency (f
EREF_CLK Width (t
Rx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In
Hold)
ETxCLK Frequency (f
ETxCLK Width (t
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 0
ETxCLK
RMII_REF_CLK
EREFCLK
ERxD1–0
ERxDV
ERxER
SCLK
= ETxCLK Period)
SCLK
MIITxCLK
ETxD3–0
ETxEN
= SCLK Frequency)
= EREFCLK Period)
= SCLK Frequency)
Figure 32. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
t
REFCLKIS
Rev. B | Page 46 of 68 | January 2011
t
ETXCLKOH
t
t
REFCLKIH
ETXCLKW
t
ETXCLKOV
t
REFCLKW
Min
None
t
4
2
EREFCLK
Min
None
t
ETxCLK
t
ETXCLK
× 40% t
× 40% t
1.8V Nominal
t
1.8V Nominal
REFCLK
V
V
DDEXT
Max
50 + 1%
DDEXT
EREFCLK
Max
25 + 1%
20
ETxCLK
× 60%
× 60%
Min
None
t
4
2
EREFCLK
Min
t
0
None
ETxCLK
2.5 V/3.3V Nominal
2.5 V/3.3V Nominal
× 35% t
× 35% t
V
V
DDEXT
Max
50 + 1%
DDEXT
Max
20
EREFCLK
25 + 1%
ETxCLK
× 65%
× 65%
Unit
MHz
ns
ns
ns
Unit
MHz
ns
ns
ns