ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 45

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DACBKEY0 Register
Name:
Address:
Default value:
Access:
DACBKEY1 Register
Name:
Address:
Default value:
Access:
Table 43. DACBCFG Write Sequence
Name
DACBKEY0
DACBCFG
DACBKEY1
POWER SUPPLY MONITOR
The power supply monitor regulates the IOV
ADuC7023. It indicates when the IOV
below a supply trip point. The monitor function is controlled
via the PSMCON register. If enabled in the IRQEN or FIQEN
register, the monitor interrupts the core using the PSMI bit in
the PSMCON MMR. This bit is immediately cleared when
CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to low supply or brownout
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
PSMCON Register
Name:
Address:
Default value:
Access:
PSMCON
0xFFFF0440
0x0008
Read/write
DACBKEY0
0xFFFF0650
0x0000
Write
DACBKEY1
0xFFFF0658
0x0000
Write
Code
0x9A
User value
0x0C
DD
supply pin drops
DD
supply on the
Rev. B | Page 45 of 96
Table 44. PSMCON MMR Bit Descriptions
Bit
3
2
1
0
COMPARATOR
The ADuC7023 integrates voltage comparators. The positive
input is multiplexed with ADC2, and the negative input has two
options: ADC3 or DAC0. The output of the comparator can be
configured to generate a system interrupt, be routed directly to
the programmable logic array, start an ADC conversion, or be
on an external pin, COMP
Hysteresis
Figure 35 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (V
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(V
H
) is ½ the width of the hysteresis range.
Name
CMP
TP
PSMEN
PSMI
P0.5/COMP
ADC2/CMP0
ADC3/CMP1
Figure 35. Comparator Hysteresis Transfer Function
COMP
OUT
Description
Comparator bit. This is a read-only bit that
directly reflects the state of the comparator.
Read 1 indicates the IOV
selected trip point, or the PSM is in power-down
mode. Read 0 indicates the IOV
below its selected trip point. This bit should be
set before leaving the interrupt service routine.
Trip point selection bits.
0 = 2.79 V.
1 = reserved.
Power supply monitor enable bit.
This bit is set to 1 to enable the power supply
monitor circuit.
This bit is cleared to 0 to disable the power
supply monitor circuit.
Power supply monitor interrupt bit. This bit is set
high by the MicroConverter once CMP goes low,
indicating low I/O supply. The PSMI bit can be
used to interrupt the processor. Once CMP
returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared once CMP goes high.
OUT
DAC0
Figure 34. Comparator
V
OS
OUT
V
H
MUX
, as shown in Figure 34.
V
H
DD
OS
supply is above its
) is the difference
CMP0
MUX
DD
ADuC7023
supply is
IRQ