ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 65

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
1
0
I
Name:
Address:
Default value:
Access:
Function:
I
Name:
Address:
Default value:
Access:
Function:
I
I2CxALT
Name:
Address:
Default value:
Access:
Function:
2
2
2
C Slave Receive Registers, I2CxSRX
C Slave Transmit Registers, I2CxSTX
C Hardware General Call Recognition Registers,
I2C0SRX, I2C1SRX
0x00
Read
These 8-bit MMRs are the I
register.
I2C0STX, I2C1STX
0x00
These 8-bit MMRs are the I
registers.
I2C0ALT, I2C1ALT
0x00
Read/write
These 8-bit MMRs are used with hardware
general calls when the I2CxSCON Bit 3 is set to 1.
These registers are used in cases where a master is
unable to generate an address for a slave, and
instead, the slave must generate the address for
the master.
0xFFFF0830, 0xFFFF0930
0xFFFF0834, 0xFFFF0934
Write
0xFFFF0838, 0xFFFF0938
Name
I2CSTFE
I2CETSTA
Description
I
This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at
the rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
I
If the I2CSETEN bit in I2CxSCON is = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in
I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission.
This bit asserts once only for a transfer.
This bit is cleared after being read.
2
2
C slave FIFO underflow status bit.
C slave early transmit FIFO status bit.
2
2
C slave receive
C slave transmit
Rev. B | Page 65 of 96
I
Name:
Addresses:
Default value:
Access:
Function:
I
I
Name:
Address:
Default value:
Access:
Function:
2
2
2
C Common Registers
C Slave Device ID Registers, I2CxIDx
C FIFO Status Registers, I2CxFSTA
I2C0FSTA, I2C1FSTA
0xFFFF084C, 0xFFFF094C
0x0000
Read/write
These 16-bit MMRs contain the status of the
Rx/Tx FIFOs in both master and slave modes.
I2C0IDx, I2C1IDx
0xFFFF093C = I2C1ID0
0xFFFF083C = I2C0ID0
0xFFFF0940 = I2C1ID1
0xFFFF0840 = I2C0ID1
0xFFFF0944 = I2C1ID2
0xFFFF0844 = I2C0ID2
0xFFFF0948 = I2C1ID3
0xFFFF0848 = I2C0ID3
0x00
bus IDs of the slave. See the I
section for further details.
Read/write
These 8-bit MMRs are programmed with I
2
C Bus Addresses
ADuC7023
2
C