ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 62

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
I
Name:
Address:
Default value:
Access:
Function:
Table 69. I2CxADR1 MMR in 10-Bit Address Mode
Bit
7 to 0
I
Name:
Address:
Default value:
Access:
Function:
Table 71. I2CxSCON MMR Bit Designations
Bit
15 to 11
10
9
8
7
6
2
2
C Address 1 Registers, I2CxADR1
C Master Clock Control Register, I2CxDIV
Name
I2CLADR
Name
I2CSTXENI
I2CSRXENI
I2CSSENI
I2CNACKEN
I2CSSEN
I2C0ADR1, I2C1ADR1
0xFFFF081C , 0xFFFF091C
0x00
Read/write
These 8-bit MMRs are used in 10-bit
addressing mode only. These registers contain
the least significant byte of the address.
I2C0DIV, I2C1DIV
0xFFFF0824, 0xFFFF0924
0x1F1F
Read/write
These MMRs control the frequency of the I
clock generated by the master on to the SCL
pin. For further details, see the I
section.
Description
These bits contain ADDR[7:0] in 10-bit
address mode.
Description
Reserved bits.
Slave transmit interrupt enable bit.
This bit is set to enable an interrupt after a slave transmits a byte.
This bit clears this interrupt source.
Slave receive interrupt enable bit.
This bit is set to enable an interrupt after the slave receives data.
This bit clears this interrupt source.
I
This bit is set to enable an interrupt on detecting a stop condition on the I
This bit clears this interrupt source.
I
This bit is set to no acknowledge the next byte in the transmission sequence.
This bit is cleared to let the hardware control the acknowledge/no acknowledge sequence.
I
This bit is set to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low
until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling
edge.
This bit is cleared to disable clock stretching.
2
2
2
C stop condition detected interrupt enable bit
C no acknowledge enable bit.
C slave SCL stretch enable bit.
2
C initial
2
Rev. B | Page 62 of 96
C
Table 70. I2CxDIV MMR
Bit
15 to 8
7 to 0
I
I
Name:
Address:
Default value:
Access:
Function:
2
2
C Slave Registers
C Slave Control Registers, I2CxSCON
Name
DIVH
DIVL
I2C0SCON, I2C1SCON
0xFFFF0828, 0xFFFF0928
0x0000
Read/write
These 16-bit MMRs configure the I
peripheral in slave mode.
These bits control the duration of the high
period of SCL.
These bits control the duration of the low
period of SCL.
Description
2
C bus.
2
C