ADV202BBCZ-150 Analog Devices Inc, ADV202BBCZ-150 Datasheet - Page 31

• Manufacturer Part Number: ADV202BBCZ-150
• Description: IC,Compression/Decompression Processor,BGA,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: JPEG2000 Video Codecr

Specifications of ADV202BBCZ-150

• Resolution (bits): 16 b
• Sigma Delta: No
• Voltage - Supply, Analog: 1.5V, 3.3V
• Voltage - Supply, Digital: 1.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL
The ADV202 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 μs before reading or writing to any
other register. If this delay is not implemented, erratic behavior
could result.
The PLL can be programmed to have any possible final
multiplier value as long as
•
•
•
•
•
•
•
•
•
•
Table 21. Recommended PLL Register Settings
IPD
0
0
0
0
1
1
1
1
Table 22. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard
SMPTE125M or ITU-R.BT656 (NTSC or PAL)
SMPTE293M (525p)
ITU-R.BT1358 (625p)
SMPTE274M (1080i)
HARDWARE BOOT
The boot mode can be configured via hardware using the CFG pins or via software (see the
after power-up is set by the CFG pins. Only Boot Mode 2, Boot Mode 4, and Boot Mode 6, described in Table 23, are available via hardware.
Table 23. Hardware Boot Modes
Boot Mode
Hardware Boot
Mode 2
Hardware Boot
Mode 4
Hardware Boot
Mode 6
JCLK > 50 MHz and < 150 MHz (144-lead version).
JCLK > 50 MHz and < 135 MHz (144-lead version).
JCLK > 50 MHz and < 115 MHz (121-lead version).
HCLK < 108 MHz (144-lead, 150 MHz version).
HCLK < 100 MHz (144-lead, 135 MHz version).
HCLK < 81 MHz (121-lead version).
JCLK ≥ 2 × VCLK for single-component input.
JCLK ≥ 2 × VCLK for YCrCb [4:2:2] input.
In JDATA mode (JDATA), JCLK must be 4 × MCLK or
higher.
For de-interlaced modes, JCLK must be ≥ 4 × MCLK.
LFB
0
0
1
1
0
0
1
1
Settings
CFG[1] tied high,
CFG[2] tied low
CFG[1] tied low,
CFG[2] tied high
CFG[1] and CFG[2]
tied high
PLLMULT
N
N
N
N
N
N
N
N
Description
No-Boot Host Mode. ADV202 does not boot, but all internal registers and memory are accessible
through normal host I/O operations.
For details, see the
SoC Boot Mode.
Reserved.
HCLKD
0
1
0
1
0
1
0
1
Rev. C | Page 31 of 40
ADV202 User’s Guide
27 MHz
27 MHz
27 MHz
74.25 MHz
CLKIN Frequency on MCLK
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To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR656
input. The PLL circuit is recommended to have a multiplier of 3.
This sets JCLK and HCLK to 81 MHz.
HCLK
N × MCLK
N × MCLK/2
2 × N × MCLK
N × MCLK
N × MCLK/2
N × MCLK/4
N × MCLK
N × MCLK/2
MCLK
The maximum burst frequency for external DMA modes is
≤0.36 JCLK.
For MCLK frequencies greater than 50 MHz, the input
clock divider must be enabled, that is, IPD set to 1.
IPD cannot be enabled for MCLK frequencies below 20 MHz.
and the
Figure 23. PLL Architecture and Control Functions
IPD
⎟
2
Getting Started with the ADV202
ADV202 User’s Guide
DETECT
PHASE
LFB
⎟
2
BYPASS
LPF
⎟
PLLMULT
JCLK
N × MCLK
N × MCLK
2 × N × MCLK
2 × N × MCLK
N × MCLK/2
N × MCLK/2
N × MCLK
N × MCLK
0x0008
0x0008
0x0008
0x0008
PLL_HI
). The first boot mode
VCO
application note.
HCLKD
PLL_LO
0x0004
0x0004
0x0004
0x0084
⎟ 2
ADV202
JCLK
HCLK