ADV7180KCP32Z-RL Analog Devices Inc, ADV7180KCP32Z-RL Datasheet - Page 45

• Manufacturer Part Number: ADV7180KCP32Z-RL
• Description: 10-bit 4x Oversampling SDTV Decoder
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180KCP32Z-RL

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
•
•
•
The HS begin (HSB) and HS end (HSE) registers allow the user
to freely position the HS output (pin) within the video line. The
values in HSB[10:0] and HSE[10:0] are measured in pixel units
from the falling edge of HS. Using both values, the user can
program both the position and length of the HS output signal.
HSB[10:0], HS Begin, Address 0x34[6:4], Address 0x35[7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 35). HSB is set to
00000000010b, which is two LLC clock cycles from count [0].
The default value of HSB[10:0] is 0x02, indicating that the HS
pulse starts two pixels after the falling edge of HS.
Table 64. HS Timing Parameters (See Figure 35)
Standard
NTSC
PAL
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
PIXEL
BUS
LLC
HS
HS Begin Adjust
HSB[10:0] (Default)
00000000010b
00000000010b
ACTIVE
VIDEO
Cr
D
E
Y
FF
00
4 LLC
EAV
HSE[10:0]
00
XY
HS End Adjust
HSE[10:0] (Default)
00000000000b
00000000000b
80
10
HSB[10:0]
80
10
H BLANK
80
Rev. F | Page 45 of 116
Figure 35. HS Timing
HS to Active Video
LLC Clock Cycles, C
in Figure 35 (Default)
272
284
10
C
Characteristic
HSE[10:0], HS End, Address 0x34[2:0], Address 0x36[7:0]
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 35). HSE is set to
00000000000b, which is 0 LLC clock cycles from count [0].
The default value of HSE[10:0] is 00, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.
For example,
•
•
•
PHS, Polarity HS, Address 0x37[7]
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active high.
When PHS is 1, HS is active low.
FF
To shift the HS toward active video by 20 LLCs, add
20 LLCs to both HSB and HSE, that is,
HSB[10:0] = [00000010110], HSE[10:0] = [00000010100].
To shift the HS away from active video by 20 LLCs, add
1696 LLCs to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
Therefore, 1696 is derived from the NTSC total number of
pixels, 1716.
To move 20 LLCs away from active video, subtract 20 from
1716 and add the result in binary to both HSB[10:0] and
HSE[10:0].
E
00
SAV
00
Active Video Samples/
Line, D in Figure 35
720Y + 720C = 1440
720Y + 720C = 1440
XY
Cb
Y
Cr
ACTIVE VIDEO
Y
D
Cb
Y
Total LLC Clock
Cycles, E in Figure 35
1716
1728
Cr
ADV7180