ADV7180KCP32Z-RL Analog Devices Inc, ADV7180KCP32Z-RL Datasheet - Page 89

• Manufacturer Part Number: ADV7180KCP32Z-RL
• Description: 10-bit 4x Oversampling SDTV Decoder
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180KCP32Z-RL

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Subaddress
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
Register
Chroma Gain
Control 2,
Chroma Gain2
(CG)
Luma Gain
Control 1, Luma
Gain1 (LG)
Luma Gain
Control 2, Luma
Gain2 (LG)
VS/FIELD
Control 1
VS/FIELD
Control 2
VS/FIELD
Control 3
HS Position
Control 1
HS Position
Control 2
HS Position
Control 3
Bit Description
CMG[7:0]/CG[7:0]; chroma
manual gain lower eight
bits; see CMG[11:8]/
CG[11:8] for description
LMG[11:8]/LG[11:8]; in
manual mode, luma gain
control can be used to
program a desired manual
luma gain; in auto mode,
it can be used to read
back the actual gain value
used
Reserved
LAGT[1:0]; luma auto
matic gain timing allows
adjustment of the luma
AGC tracking speed
LMG[7:0]/LG[7:0]; luma
manual gain lower eight
bits; see LMG[11:8]/
LG[11:8] for description
Reserved
HVSTIM; selects where
within a line of video the
VS signal is asserted
NEWAVMODE; sets the
EAV/SAV mode
Reserved
Reserved
VSBHE
VSBHO
Reserved
VSEHE
VSEHO
HSE[10:8]; HS end allows
positioning of the HS
output within the
video line
Reserved
HSB[10:8]; HS begin
allows positioning of
the HS output within
the video line
Reserved
HSB[7:0]; see Address 0x34,
using HSB[10:0] and
HSE[10:0], users can
program the position
and length of the HS
output signal
HSE[7:0]; see Address
0x35 description
7
0
0
0
1
1
x
0
0
1
0
1
0
0
0
(Shading Indicates Default State)
6
0
0
1
0
1
x
0
0
1
0
1
0
0
0
Rev. F | Page 89 of 116
5
0
1
x
0
0
0
0
0
0
4
0
1
x
0
1
0
0
0
0
0
Bits
3
0
x
x
0
1
0
0
0
0
0
2
0
x
x
0
0
1
0
0
0
1
0
x
x
1
0
0
0
1
0
0
0
x
x
0
1
0
0
0
0
Comments
CMG[11:0] = see the CMG section
CMG[11:0] = see the CMG section
LAGC[1:0] settings decide in which
mode LMG[11:0] operates
Set to 1
Fast (TC = 0.2 sec)
Adaptive
LMG[11:0] - see the LMG section
LMG[11:0] =- see the LMG section
Set to default
Start of line relative to HSE
Start of line relative to HSB
EAV/SAV codes generated to suit
Analog Devices encoders
Manual VS/FIELD position controlled by
the 0x32, 0x33, and 0xE5 to 0xEA registers
VS goes high in the middle of the
line (even field)
VS changes state at the start of the
line (even field)
VS goes high in the middle of the
line (odd field)
VS changes state at the start of the
line (odd field)
Set to default
VS goes low in the middle of the
line (even field)
VS changes state at the start of the
line (even field)
VS goes low in the middle of the line
(odd field)
VS changes state at the start of the
line odd field
HS output ends HSE[10:0] pixels after
the falling edge of HSYNC
Set to 0
HS output starts HSB[10:0] pixels
after the falling edge of HSYNC
Set to 0
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Set to default
Set to default
Notes
Min value = 0d,
Max value = 4095d
Only has an effect
if LAGC[1:0] is set
to autogain (001,
010, 011, or 100)
Min value = 1024d,
Max value = 4095d
HSE = HSYNC end
HSB = HSYNC begin
NEWAVMODE bit
must be set high
NEWAVMODE bit
must be set high
Using HSB and
HSE the user can
program the
position and length
of the output
HSYNC
ADV7180