ADV7183BBSTZ Analog Devices Inc, ADV7183BBSTZ Datasheet - Page 47

• Manufacturer Part Number: ADV7183BBSTZ
• Description: IC,TV/VIDEO CIRCUIT,Color Decoder Circuit,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183BBSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VBI DATA DECODE
The following low data rate VBI signals can be decoded by the
ADV7183B:
•
•
•
•
•
The presence of any of the above signals is detected and, if
applicable, a parity check is performed. The result of this testing
is contained in a confidence bit in the VBI Info[7:0] register.
Users are encouraged to first examine the VBI Info register
before reading the corresponding data registers. All VBI data
decode bits are read only.
All VBI data registers are double-buffered with the field signals.
This means that data is extracted from the video lines and
appears in the appropriate I
transition. They are then static until the next field.
The user should start an I
examining the VBI Info register. Then, depending on what data
was detected, the appropriate data registers should be read.
Note that the data registers are filled with decoded VBI data
even if their corresponding detection bits are low; it is likely
that bits within the decoded data stream are wrong.
The closed captioning data (CCAP) is available in the I
registers and is also inserted into the output video data stream
during horizontal blanking.
The Gemstar-compatible data is not available in the I
registers and is inserted into the data stream only during
horizontal blanking.
WSSD Wide Screen Signaling Detected, Address 0x90[0]
Logic 1 for this bit indicates the data in the WSS1 and WSS2
registers is valid.
The WSSD bit goes high if the rising edge of the start bit is
detected within a time window and if the polarity of the parity
bit matches the data transmitted.
When WSSD is 0, no WSS is detected and confidence in the
decoded data is low.
When WSSD is 1, WSS is detected and confidence in the
decoded data is high.
Wide screen signaling (WSS)
Copy generation management systems (CGMS)
Closed captioning (CCAP)
EDTV
Gemstar 1×- and 2×-compatible data recovery
2
C read sequence with VS by first
2
C registers with the next field
2
C
2
C
Rev. B | Page 47 of 100
CCAPD Closed Caption Detected, Address 0x90[1]
A Logic 1 for this bit indicates that the data in the CCAP1 and
CCAP2 registers is valid.
The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window and if the polarity of the parity
bit matches the data transmitted.
When CCAPD is 0, no CCAP sequences are detected and
confidence in the decoded data is low.
When CCAPD is 1, the CCAP sequence is detected and
confidence in the decoded data is high.
EDTVD EDTV Sequence Detected, Address 0x90[2]
A Logic 1 for this bit indicates the data in the EDTV1, 2, 3
registers is valid.
The EDTVD bit goes high if the rising edge of the start bit is
detected within a time window and if the polarity of the parity
bit matches the data transmitted.
When EDTVD is 0, no EDTV sequence is detected and
confidence in the decoded data is low.
When EDTVD is 1, an EDTV sequence is detected and
confidence in the decoded data is high.
CGMSD CGMS-A Sequence Detected, Address 0x90[3]
Logic 1 for this bit indicates that the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
checksum has been calculated from a received CGMS packet.
When CGMSD is 0, no CGMS transmission is detected and
confidence in the decoded data is low.
When CGMSD is 1, the CGMS sequence is decoded and
confidence in the decoded data is high.
CRC_ENABLE CRC, Address 0xB2[2]
For certain video sources, the CRC data bits can have an invalid
format. In these circumstances, the CRC checksum validation
procedure can be disabled. The CGMSD bit goes high if the
rising edge of the start bit is detected within a time window.
When CRC_ENABLE is 0, no CRC check is performed. The
CGMSD bit goes high if the rising edge of the start bit is
detected within a time window.
When CRC_ENABLE is 1 (default), CRC checksum is used to
validate the CGMS sequence. The CGMSD bit goes high for a
valid checksum. The default is ADI’s recommended setting.
ADV7183B