AM29DL323GB90EI AMD (ADVANCED MICRO DEVICES), AM29DL323GB90EI Datasheet - Page 14

• Manufacturer Part Number: AM29DL323GB90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29DL323GB90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Supply Voltage Max: 3.6V
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Supply Voltage: 3V

dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
12
CC5
Am29DL322G
Am29DL323G
Am29DL324G
Part Number
IL
in the DC Characteristics table represents the
Device
but not within V
Megabits
SS
16 Mbit
4 Mbit
8 Mbit
±0.3 V, the standby current will
CC4
SS
). If RESET# is held
±0.3 V, the device
thirty-one 64 Kbyte/32 Kword
fifteen 64 Kbyte/32 Kword
seven 64 Kbyte/32 Kword
Table 2. Device Bank Divisions
Bank 1
Eight 8 Kbyte/4 Kword,
Eight 8 Kbyte/4 Kword,
Eight 8 Kbyte/4 Kword,
D A T A
Sector Sizes
RP
, the
Am29DL32xG
S H E E T
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V
I
reset current. Also refer to AC Characteristics tables
for RESET# timing parameters and to Figure 14 for the
timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
CC4
in the DC Characteristics table represents the
READY
Megabits
28 Mbit
24 Mbit
16 Mbit
(during Embedded Algorithms). The sys-
READY
IH
.
(not during Embedded Algo-
IH
Bank 2
, output from the device is
25686B10 December 4, 2006
64 Kbyte/32 Kword
64 Kbyte/32 Kword
64 Kbyte/32 Kword
Sector Sizes
Forty-eight
Thirty-two
Fifty-six
RH
after the RE-