AM29LV320DT90EI AMD (ADVANCED MICRO DEVICES), AM29LV320DT90EI Datasheet - Page 21

• Manufacturer Part Number: AM29LV320DT90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Once the SecSi Sector is locked and verified,
the system must write the Exit SecSi Sector
Region command sequence to return to reading
and writing the remainder of the array.
The SecSi Sector protection must be used with
caution since, once protected, there is no pro-
cedure available for unprotecting the SecSi
Sector area and none of the bits in the SecSi
Sector memory space can be modified in any
way.
Hardware Data Protection
The command sequence requirement of unlock
cycles for programming or erasing provides
data protection against inadvertent writes (re-
fer to
nitions). In addition, the following hardware
data protection measures prevent accidental
erasure or programming, which might other-
wise be caused by spurious system level signals
during V
tions, or from system noise.
Low V
When V
accept any write cycles. This protects data dur-
ing V
mand register and all internal program/erase
circuits are disabled, and the device resets to
the read mode. Subsequent writes are ignored
November 15, 2004
Figure 3. SecSi Sector Protect Verify
CC
Table 14, on page 29
CC
CC
power-up and power-down. The com-
Write 40h to SecSi
CC
Read from SecSi
Write Inhibit
Sector address
Sector address
is less than V
A1 = 1, A0 = 0
A1 = 1, A0 = 0
Write 60h to
with A6 = 0,
any address
with A6 = 0,
RESET# =
power-up and power-down transi-
V
Wait 1 µs
START
IH
or V
ID
LKO
Remove V
, the device does not
SecSi Sector is
SecSi Sector is
If data = 00h,
If data = 01h,
from RESET#
Protect Verify
SecSi Sector
unprotected.
Write reset
for command defi-
protected.
command
complete
IH
or V
ID
Am29LV320D
until V
provide the proper signals to the control pins to
p reven t un inte ntion al w rite s w hen V
greater than V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE# = V
a write cycle, CE# and WE# must be a logical
zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
power up, the device does not accept com-
mands on the rising edge of WE#. The internal
state machine is automatically reset to the read
mode on power-up.
COMMON FLASH MEMORY
INTERFACE (CFI)
The Common Flash Interface (CFI) specification
outlines device and host system software inter-
rogation handshake, which allows specific ven-
dor-specified software algorithms to be used
for entire families of devices. Software support
can then be device-independent, JEDEC ID-in-
dependent, and forward- and backward-com-
patible for the specified flash device families.
Flash vendors can standardize their existing in-
terfaces for long-term compatibility.
This device enters the CFI Query mode when
the system writes the CFI Query command,
98h, to address 55h in word mode (or address
AAh in byte mode), any time the device is
ready to read array data. The system can read
CFI information at the addresses given in
Table 9, on page 22
page
system must write the reset command.
The system can also write the CFI query com-
mand when the device is in the autoselect
mode. The device enters the CFI query mode,
and the system can read CFI data at the ad-
dresses given in
Table 12, on page
the reset command to return the device to the
reading array data.
For further information, please refer to the CFI
Specification and CFI Publication 100, available
v i a
http://www.amd.com/flash/cfi. Alternatively,
contact an AMD representative for copies of
these documents.
24. To terminate reading CFI data, the
CC
t h e
IL
is greater than V
, CE# = V
LKO
Wo r l d
.
Table 9, on page 22
24. The system must write
IH
IL
or WE# = V
and OE# = V
through
LKO
W i d e
. The system must
Table 12, on
IH
. To initiate
We b
IH
through
during
C C
a t
21
is