AM29LV320DT90EI AMD (ADVANCED MICRO DEVICES), AM29LV320DT90EI Datasheet - Page 27

• Manufacturer Part Number: AM29LV320DT90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip
erase command sequence is initiated by writing
two unlock cycles, followed by a set-up com-
mand. Two additional unlock write cycles are
then followed by the chip erase command,
which in turn invokes the Embedded Erase al-
gorithm. The device does not require the sys-
t e m t o p r e p r o g r a m p r i o r t o e r a s e . T h e
Embedded Erase algorithm automatically pre-
programs and verifies the entire memory for an
all zero data pattern prior to electrical erase.
The system is not required to provide any con-
trols or tim ing s during the se operatio ns.
Table 14, on page 29
data requirements for the chip erase command
sequence. Note that the autoselect, SecSi Sec-
tor, and CFI modes are unavailable while an
erase operation is in progress.
November 15, 2004
Note: See
command sequence.
Increment Address
Figure 4. Program Operation
Table 14, on page 29
Embedded
in progress
algorithm
Program
No
shows the address and
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
for program
START
Yes
Yes
No
Am29LV320D
When the Embedded Erase algorithm is com-
plete, the device returns to the read mode and
addresses are no longer latched. The system
can determine the status of the erase operation
by using DQ7, DQ6, DQ2, or RY/BY#. Refer to
“Write Operation Status” on page 30
mation on these status bits.
Any commands written during the chip erase
operation are ignored. However, note that a
hardware reset immediately terminates the
erase operation. If that occurs, the chip erase
command sequence should be reinitiated once
the device returns to reading array data, to en-
sure data integrity.
Figure 5, on page 28
for the erase operation. Refer to table
and Program Operations” on page 41
rameters, and
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The
sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up
command. Two additional unlock cycles are
written, and are then followed by the address
of the sector to be erased, and the sector erase
command.
dress and data requirements for the sector
erase command sequence. Note that the au-
toselect, SecSi Sector, and CFI modes are un-
a v a i l a b l e w h i l e a n e r a s e o p e r a t i o n i s i n
progress.
The device does not require the system to pre-
program prior to erase. The Embedded Erase
algorithm automatically programs and verifies
the entire memory for an all zero data pattern
prior to electrical erase. The system is not re-
quired to provide any controls or timings during
these operations.
After the command sequence is written, a sec-
tor erase time-out of 50 µs occurs. During the
time-out period, additional sector addresses
and sector erase commands may be written.
Loading the sector erase buffer may be done in
any sequence, and the number of sectors may
be from one sector to all sectors. The time be-
tween these additional cycles must be less than
50 µs, otherwise the last address and com-
mand may not be accepted, and erasure may
begin. It is recommended that processor inter-
rupts be disabled during this time to ensure all
commands are accepted. The interrupts can be
re-enabled after the last Sector Erase com-
mand is written. Any command other than
Sector Erase or Erase Suspend during the
Table 14, on page 29
Figure 19, on page 43
illustrates the algorithm
shows the ad-
section for
for infor-
for pa-
“Erase
27