CRD42L51 Cirrus Logic Inc, CRD42L51 Datasheet - Page 42

• Manufacturer Part Number: CRD42L51
• Description: Ref Bd Low-voltage Stereo Codec
• Manufacturer: Cirrus Logic Inc

42
4.9
1. Audible pops.
Power Off Transition
Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the CODEC in standby,
1. Mute the DAC’s and ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a
3. Bring RESET low.
fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary
to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.
1. Pops suppressed.
Reset Transition
ERROR: Power removed
Hardware Mode
Minimal feature
set support.
1. No audio signal generated.
2. Control Port Registers reset
to default.
No
Off Mode (Power Applied)
1. No audio signal
generated.
Control Port Valid
Write Seq. within
RESET = Low?
Control Port
No Power
10 ms?
Active
No
ERROR: MCLK/LRCK ratio change
Registers setup to
Figure 22. Initialization Flowchart
desired settings.
Software Mode
Yes
Yes
RESET = Low
Audio signal generated per control port or stand-
1. Aout bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
No
ERROR: MCLK removed
Analog Output Freeze
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Sub-Clocks Applied
ADC Initialization
Normal Operation
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
MCLK cycle delay
MCLK Applied?
PDN bit = '1'b?
Digital/Analog
Output Muted
alone settings.
Charge Caps
2048 internal
MCLK/LRCK
20 ms delay
Ratio?
Valid
Valid
Yes
No
Yes
No
DAC Initialization
Headphone Amp
Charge Pump
PDN bit set to '1'b
(software mode only)
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50 ms delay
20
µ
s delay
1. No audio signal generated.
2. Control Port Registers retain
settings.
1. Pops suppressed.
Headphone Amp
20
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Standby Mode
µ
Transition
Stand-By
s delay (DAC
CS42L51
only)
DS679F1