CS61584A-IQ3Z Cirrus Logic Inc, CS61584A-IQ3Z Datasheet - Page 21
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CS61584A-IQ3Z
Manufacturer Part Number
CS61584A-IQ3Z
Description
IC,Line Interface,QFP,64PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS61584A-IQ3Z.pdf
(54 pages)
Specifications of CS61584A-IQ3Z
Interface
Parallel/Serial
Voltage - Supply
3.3V, 5V
Package / Case
64-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1713
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS61584A-IQ3Z
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS61584A-IQ3Z
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
CS61584A-IQ3ZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
8.3
During Host mode operation, a bipolar violation
(BPV) is detected by the receiver and reported us-
ing the Latched-BPV bit in the Status registers. If
CODER = 1 in the Control A registers, the RNEG
pin becomes the BPV output strobe pin that is set
high for one bit period on detection of a BPV. Note
that B8ZS (or HDB3) zero substitutions are not
flagged as bipolar violations if the B8ZS (or
HDB3) decoder has been enabled (CODER = 1 and
AMI-R = 0 in the Control A registers).
8.4
During Host mode operation if CODER = 1 and
EXZ = 1 in the Control A register, the BPV output
pin is OR’ed with receive excessive zero events. In
AMI mode when AMI-Rx = 1, the BPV pin is set
high for one bit period when 16 or more consecu-
tive zeros are received. In B8ZS mode when AMI-
Rx = 0, the BPV pin is set high for one bit period
when 8 or more consecutive zeros are received.
This is in accordance with the ANSI T1.231 speci-
fication. For E1 operation with HDB3 disabled, the
excessive zeros detection is also disabled. For E1
with HDB3 enabled the BPV pin goes high for ev-
ery set of 4 consecutively received zeros.
8.5
During Hardware mode and Host mode operation,
the loss of signal (LOS) condition is detected by the
receiver and reported when the LOS pin is set high.
Loss of signal is indicated when 175 ±15 consecu-
tive zeros are received, or when the receive
(RTIP/RRING) signal level drops below the receiv-
er sensitivity of the device. The LOS condition is
exited according to the ANSI T1.231-1993 criteria
that requires a minimum 12.5% ones density signal
over 175 ±75 bit periods with no more than 100
consecutive zeros. During LOS, recovered data is
squelched and zeroes are output on RPOS/RNEG
(RDATA).
DS261PP5
DS261F1
Bipolar Violation Detection
Excessive Zeros Detection
Loss of Signal
DS261PP5
During Host mode operation, LOS is reported us-
ing the LOS and Latched-LOS bits in the Status
registers. Note that both the LOS pin and register
indications are available in Host mode operation.
The LOS pin and/or bit is set high when the device
is reset, in power-up, or a channel is powered-down
and returns low when data is recovered by the re-
ceiver.
During LOS condition the RPOS (RDATA),
RNEG pins are forced low, except when LLOOP1
(digital loopback) is enabled, or when the AAO
(Automatic All Ones) bit is set in the channel 1
mask register. Setting the AAO bit high forces un-
framed all ones pattern out on the RPOS (RDA-
TA), RNEG pins when LOS condition occurs.
When the jitter attenuator is in the receive path and
LOS occurs, the frequency of the last valid recov-
ered signal is held at RCLK. When the jitter atten-
uator is not in the receive path, the output
frequency becomes the frequency of the reference
clock.
8.6
During Hardware mode operation, transmit all ones
(TAOS) is selected by setting the TAOS pin high.
During Host mode, TAOS is controlled using the
TAOS bit in the Control B registers.
Selecting TAOS causes continuous ones to be
transmitted to the line on TTIP and TRING at the
frequency of REFCLK. In this mode, the transmit
data inputs TPOS and TNEG (or TDATA) are ig-
nored. A TAOS request overrides the data transmit-
ted to the line interface during local and remote
loopbacks. Note that the CLKLOST interrupt is
not available for TCLK in the TAOS mode.
8.7
During Host mode operation, the data at RPOS and
RNEG (or RDATA) may be forced to output an un-
framed all-ones pattern by setting both the
LLOOP1 and LLOOP2 bits in the Control B regis-
ter to "1". An automatic Receive All Ones (AAO)
Transmit All Ones
Receive All Ones
CS61584A
CS61584A
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