CS61584A-IQ3Z Cirrus Logic Inc, CS61584A-IQ3Z Datasheet - Page 8
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CS61584A-IQ3Z
Manufacturer Part Number
CS61584A-IQ3Z
Description
IC,Line Interface,QFP,64PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS61584A-IQ3Z.pdf
(54 pages)
Specifications of CS61584A-IQ3Z
Interface
Parallel/Serial
Voltage - Supply
3.3V, 5V
Package / Case
64-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1713
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS61584A-IQ3Z
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS61584A-IQ3Z
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
CS61584A-IQ3ZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
8
DIGITAL CHARACTERISTICS
Notes: 23. Digital inputs are designed for CMOS logic levels.
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = DV+.)
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be
8
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (I
Low-Level Output Voltage (I
Input Leakage Current (Digital pins except J-TMS and J-TDI)
T1 Clock/Data
TCLK Frequency
TCLK Duty Cycle
RCLK Duty Cycle
Rise Time (All Digital Outputs)
Fall Time (All Digital Outputs)
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
E1 Clock/Data
TCLK Frequency
TCLK Duty Cycle
RCLK Duty Cycle
Rise Time (All Digital Outputs)
Fall Time (All Digital Outputs)
RPOS/RNEG (RDATA) to RCLK Rising Setup Time
RCLK Rising to RPOS/RNEG (RDATA) Hold Time
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
24. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.
26. RCLK duty cycle may be outside the specified limits when the jitter attenuator is in the transmit path
27. At max load of 50 pF.
tolerated by the CS61584A, the jitter attenuator must be switched to the transmit path of the line
interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p.
and when the jitter attenuator is employing the overflow/underflow protection mechanism.
Parameter
Parameter
out
out
= 1.6 mA)
= -40 µA)
(T
A
= -40 to 85 °C; power supply pins within ±5% of nominal.)
DS261PP5
(T
(Note 23)
(Note 23)
(Note 24)
(Note 24)
(Note 25)
(Note 26) t
(Note 27)
(Note 27)
(Note 25)
(Note 26) t
(Note 27)
(Note 27)
A
= -40 to 85 °C; power supply pins within ±5% of nominal;
t
t
Symbol
Symbol
pwh2
pwh1
pwh2
pwh1
V
V
t
t
V
f
t
f
t
V
t
t
t
t
su1
su2
su1
su2
tclk
tclk
OH
t
h1
h2
t
h1
h2
OL
t
t
IH
IL
r
f
r
f
/t
/t
/t
/t
pw2
pw1
pw2
pw1
(DV+) - 0.5
(DV+) - 0.3
Min
20
45
25
25
20
45
25
25
-
-
-
-
-
-
-
-
-
-
Min
-
-
-
1.544
2.048
Typ
274
274
194
194
50
50
50
50
-
-
-
-
-
-
-
-
Max
±10
0.5
0.3
CS61584A
CS61584A
-
-
Max
80
55
65
65
80
55
65
65
-
-
-
-
-
-
-
-
-
-
DS261PP5
DS261F1
MHz
MHz
Unit
Unit
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
V
V
V
V