CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 31

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

DS692PP1
6.3
6.3.1
6.3.2
6.4
Note:
1. If RXP/N[1:0] is selected by either the receiver MUX or the TX pass-through MUX, N=1.
2. If RXP/N[1:0] is selected by both the receiver MUX and the TX pass-through MUX, N=2.
3. If RXP/N[1:0] is not selected at all, N=0 (i.e. high impedance).
Recovered Master Clock - RMCK
The CS8422 has an internal PLL which recovers a high-frequency system clock, referred to as the recov-
ered master clock (RMCK). RMCK can be generated by incoming AES3-compatible data or the ISCLK
(slave mode and Software Mode only). This clock is used as the master clock source for the AES3 receiver
and the master-mode serial port that it directly supplies data to, and is available as an output on the RMCK
pin. In addition, the user can set the RMCK as the master clock of either of the two remaining serial ports.
XTI System Clock Mode
A special clock switching mode is available that allows the clock present at the XTI-XTO clock input to au-
tomatically replace RMCK when the PLL becomes unlocked. This is accomplished without spurious transi-
tions or glitches on RMCK.
When clock switching is enabled, the PLL’s loss of lock will cause the XTI-XTO clock input to be output on
RMCK. If a serial port is set master mode and has RMCK as its master clock source, it’s LRCK and SCLK
Hardware Mode Control
In Hardware Mode, the RMCK frequency is determined by the incoming AES3 frame rate and the
MS_SEL pin. RMCK can be routed for use as the master clock for the serial audio output associated with
SDOUT1 by connecting a 20 kΩ resistor from the RMCK pin to VL. See
page 39
Software Mode Control
In Software Mode, The RMCK frequency is determined by the incoming AES3 frame rate or ISCLK/64
(slave mode only). The RMCK frequency is configured in the register described in
ered Master Clock Ratio Control & Misc. (09h)” on page
CK, then the ratios in the
of 64*RMCK/ISCLK.
R X N [1:0 ]
R X P [1:0 ]
for more details.
(1 5 0 0 + 1 5 0 0 /N ) Ω
(1 5 0 0 + 1 5 0 0 /N ) Ω
Figure 18. Differential Receiver Input Structure
“Recovered Master Clock Ratio Control & Misc. (09h)”
(2 2 0 0 0 /N ) Ω
(2 2 0 0 0 /N ) Ω
52. If the ISCLK is chosen as the source for RM-
A G N D
V A
(2 2 0 0 0 /N ) Ω
(2 2 0 0 0 /N ) Ω
+
-
“Hardware Mode Control” on
register reflect the ratio
Section 11.9 “Recov-
CS8422
31