CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 50

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

50
11.5
11.6
11.7
GPO0SEL3
GPO2SEL3
SAI_CLK3
7
0
7
0
7
0
GPO Control 1 (05h)
GPOxSEL[3:0] – GPO Source select for GPO0 and GPO1 pins. See
GPO[3:0].
GPO Control 2 (06h)
GPOxSEL[3:0] – GPO Source select for GPO2 and GPO3 pins. See
GPO[3:0].
Serial Audio Input Clock Control (07h)
SAI_CLK[3:0] – Selects the serial audio input master clock-to-ILRCK ratio when the serial audio input port
is set to master mode (SIMS = 1 as shown in
a serial audio output is sourced directly by the serial audio input port, SAI_CLK[3:0] determine the
MCLK/LRCK ratio for both serial ports if they are set to master mode.
SRC_UNLOCK
0000 - ILRCK = MCLK/64
Function
XTI_OUT
192KHZ
NVERR
VLRCK
96KHZ
AUDIO
EMPH
RERR
RCBL
GND
INT
VL
TX
C
U
SAI_CLK2
GPO0SEL2
GPO2SEL2
6
1
6
0
6
0
Code
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
SAI_CLK1
GPO0SEL1
GPO2SEL1
5
0
5
0
5
0
Fixed low level
Fixed VL level.
State of EMPH bit in the incoming data stream
CS8422 interrupt output
Channel status bit
User data bit
Receiver Error
Non-Validity Receiver Error
Receiver Channel Status Block
Defined in
Defined in
Non-audio indicator for decoded input stream
Virtual LRCK, can be used to frame the C and U output data.
Pass through of AES/SPDIF input selected by TXSEL[2:0] in
“Receiver Input Control (03h)” on page
SRC unlock indicator
Buffered XTI-XTO output
Table 7. GPO Pin Configurations
SAI_CLK0
GPO0SEL0
GPO2SEL0
“PLL Status (15h)” on page
“PLL Status (15h)” on page
4
0
4
0
4
0
“Serial Audio Input Data Format (0Bh)” on page
SAI_MCLK
GPO1SEL3
GPO3SEL3
3
0
3
0
3
0
Definition
60.
60.
48.
GPO1SEL2
GPO3SEL2
Reserved
2
2
0
2
0
Table 7
Table 7
GPO1SEL1
GPO3SEL1
Reserved
for available outputs for
for available outputs for
Section 11.3
1
1
0
1
0
GPO1SEL0
GPO3SEL0
53). Note: if
CS8422
Reserved
DS692PP1
0
0
0
0
0